Time-Base Period Shadow Register | Texas Instruments TMS320x28xx

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Time-Base (TB) Submodule

Figure 2-3. Time-Base Frequency and Period

TPWM

4

3

2

1

0

1

0

2

3

		PRD
4	4
	3

2

Z1

0

For Up Count and Down Count

TPWM

4

3

2

1

0

4

3

PRD 4

3

2

1

0

2

1 Z

0

TPWM = (TBPRD + 1) x TTBCLK FPWM = 1/ (TPWM)

		TPWM									TPWM
4								4
3					3			3					3
3					3			3					3
2						2		2						2
1							1	1							1
0								0

For Up and Down Count

TPWM = 2 x TBPRD x TTBCLK

FPWM = 1 / (TPWM)

0

CTR_dir

Up

Down

Up

Down

2.2.3.1Time-Base Period Shadow Register

The time-base period register (TBPRD) has a shadow register. Shadowing allows the register update to be synchronized with the hardware. The following definitions are used to describe all shadow registers in the ePWM module:

∙Active Register

The active register controls the hardware and is responsible for actions that the hardware causes or invokes.

∙Shadow Register

The shadow register buffers or provides a temporary holding location for the active register. It has no direct effect on any control hardware. At a strategic point in time the shadow register's content is transferred to the active register. This prevents corruption or spurious operation due to the register being asynchronously modified by software.

The memory address of the shadow period register is the same as the active register. Which register is written to or read from is determined by the TBCTL[PRDLD] bit. This bit enables and disables the TBPRD shadow register as follows:

∙Time-Base Period Shadow Mode:

The TBPRD shadow register is enabled when TBCTL[PRDLD] = 0. Reads from and writes to the

TBPRD memory address go to the shadow register. The shadow register contents are transferred to the active register (TBPRD (Active) ← TBPRD (shadow)) when the time-base counter equals zero (TBCTR = 0x0000). By default the TBPRD shadow register is enabled.

∙Time-Base Period Immediate Load Mode:

If immediate load mode is selected (TBCTL[PRDLD] = 1), then a read from or a write to the TBPRD memory address goes directly to the active register.

26

ePWM Submodules

SPRU791D–November 2004–Revised October 2007

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Image 26

Texas Instruments TMS320x28xx, 28xxx manual Time-Base Period Shadow Register, ∙ Active Register, ∙ Shadow Register

Contents

Reference Guide Submit Documentation Feedback Contents Controlling a 3-Phase Interleaved DC/DC Converter List of Figures Event-Trigger Socb Pulse Generator Simplified ePWM Module List of Tables Submit Documentation Feedback CPU Users Guides Related Documentation From Texas InstrumentsData Manuals Peripheral Guides Tools Guides Application Reports Trademarks TMS320C28x, C28x are trademarks of Texas Instruments Submit Documentation Feedback Introduction Introduction Submodule Overview Multiple ePWM Modules ∙ ADC start-of-conversion signals EPWMxSOCA and EPWMxSOCB ∙ PWM output signals EPWMxA and EPWMxB∙ Trip-zone signals TZ1 to TZ6 ∙ Peripheral Bus EPWM Submodules and Critical Internal Signal Interconnects Register Mapping Time-Base Submodule Registers Offset Size NameDescription Counter-Compare Submodule Registers EPWM Submodules Overview Submodule Configuration ParametersSubmodule Configuration Parameter or Option Example 2-1. Constant Definitions Used in the Code Examples Tbup Chpenable Time-Base TB Submodule Purpose of the Time-Base Submodule Register Controlling and Monitoring the Time-base SubmoduleTime-Base Submodule Registers ∙ Up-Count Mode Key Time-Base Signals∙ Up-Down-Count Mode ∙ Down-Count Mode Time-Base Period Shadow Register ∙ Time-Base Period Shadow Mode∙ Time-Base Period Immediate Load Mode ∙ Active Register Time-Base Counter Synchronization Time-Base Counter Synchronization Scheme EPWM11SYNCI EPWM11SYNCO ∙ EPWMxSYNCI Synchronization Input Pulse ∙ Software Forced Synchronization Pulse Phase Locking the Time-Base Clocks of Multiple ePWM Modules Time-base Counter Modes and Timing Waveforms Time-Base Down-Count Mode Waveforms Counter-Compare CC Submodule 11. Counter-Compare Submodule Counter-Compare Submodule Registers Purpose of the Counter-Compare SubmoduleControlling and Monitoring the Counter-Compare Submodule Register Name Address Offset ∙ Shadow Mode Count Mode Timing WaveformsCounter-Compare Submodule Key Signals ∙ Immediate Load Mode CTR=CMPA CTR=CMPB CTR = Cmpb Action-Qualifier Submodule Registers Action-Qualifier AQ SubmodulePurpose of the Action-Qualifier Submodule ∙ Clear Low Action-Qualifier Submodule Possible Input Events∙ Set High ∙ Toggle TB Counter equals Actions 10. Action-Qualifier Event Priority for Down-Count Mode Action-Qualifier Event Priority for Up-Down-Count ModeAction-Qualifier Event Priority for Up-Count Mode Action-Qualifier Event Priority Use up-down-count mode to generate an asymmetric PWM Waveforms for Common ConfigurationsUse up-down-count mode to generate a symmetric PWM When using up-count mode to generate an asymmetric PWM 20. Up-Down-Count Mode Symmetrical Waveform Example 2-2. Code Sample for Figure Tbctr Value EPWMxA EPWMxB Example 2-3. Code Sample for Figure Tbclk = Sysclkout Example 2-4. Code Sample for Figure EdgePosA Example 2-5. Code Sample for Figure Example 2-6. Code Sample for Figure Tbctr Example 2-7. Code Sample for Figure EPWMxA EPWMxB Controlling and Monitoring the Dead-Band Submodule Dead-Band Generator DB SubmodulePurpose of the Dead-Band Submodule 12. Dead-Band Generator Submodule Registers ∙ Input Source Selection ∙ Output Mode ControlOperational Highlights for the Dead-Band Submodule ∙ Polarity Control Mode Description 13. Classical Dead-Band Operating Modes 29. Dead-Band Waveforms for Typical Cases 0% Duty 100% Dead-Band Delay in μS FED = Dbfed × Ttbclk RED = Dbred × Ttbclk Controlling the PWM-Chopper Submodule PWM-Chopper PC SubmodulePurpose of the PWM-Chopper Submodule Operational Highlights for the PWM-Chopper Submodule Waveforms 31. PWM-Chopper Submodule Operational Details OSHTWTHz One-Shot Pulse16. Possible Pulse Width Values for Sysclkout = 100 MHz Duty Cycle Control Period Trip-Zone TZ Submodule Purpose of the Trip-Zone Submodule 17. Trip-Zone Submodule Registers Controlling and Monitoring the Trip-Zone SubmoduleOperational Highlights for the Trip-Zone Submodule ∙ Cycle-by-Cycle CBC Scenario a Example 2-8. Trip-Zone Configurations18. Possible Actions On a Trip Event Scenario B 36. Trip-Zone Submodule Mode Control Logic Generating Trip Event Interrupts Event-Trigger ET Submodule 37. Trip-Zone Submodule Interrupt Logic Operational Overview of the Event-Trigger Submodule 19. Event-Trigger Submodule Registers CTR=CMPB CTRD=CMPB 41. Event-Trigger Interrupt Generator 42. Event-Trigger Soca Pulse Generator Submit Documentation Feedback Applications to Power Topologies Controlling Multiple Buck Converters With Independent Key Configuration Capabilities Overview of Multiple Modules CTR=0 EPWM1B CTR=CMPB Control of Four Buck Stages. Here FPWM1≠ FPWM2≠ FPWM3≠ FPWM4 Buck Waveforms for -3Note Only three bucks shown here Example 3-1. Configuration for Example in Figure 500 Controlling Multiple Buck Converters With Same Frequencies Control of Four Buck Stages. Note FPWM2 = N x FPWM1 Buck Waveforms for -5Note FPWM2 = FPWM1 Example 3-2. Code Snippet for Configuration in Figure Controlling Multiple Half H-Bridge HHB Converters Control of Two Half-H Bridge Stages FPWM2 = N x FPWM1 Half-H Bridge Waveforms for -7Note Here FPWM2 = FPWM1 Controlling Dual 3-Phase Inverters for Motors ACI and Pmsm Example 3-3. Code Snippet for Configuration in Figure EPWM1A 10 -Phase Inverter Waveforms for -9Only One Inverter Shown Example 3-4. Code Snippet for Configuration in Figure 11. Configuring Two PWM Modules for Phase Control Controlling a 3-Phase Interleaved DC/DC Converter Controlling a 3-Phase Interleaved DC/DC Converter 13. Control of a 3-Phase Interleaved DC/DC Converter 14 -Phase Interleaved DC/DC Converter Waveforms for Figure Example 3-5. Code Snippet for Configuration in Figure 15. Controlling a Full-H Bridge Stage FPWM2 = FPWM1 16. ZVS Full-H Bridge Waveforms Example 3-6. Code Snippet for Configuration in Figure Submit Documentation Feedback Trip-Zone Submodule Control and Status Registers Proper Interrupt Initialization ProcedurePWM-Chopper Submodule Control Register Time-Base Period Register Tbprd Field Descriptions Time-Base Phase Register Tbphs Field DescriptionsTime-Base Submodule Registers Time-Base Counter Register Tbctr Field Descriptions Time-Base Control Register Tbctl Field Descriptions Bit Field Value Description Software Forced Synchronization Pulse Bit Field Counter-Compare Submodule RegistersTime-Base Status Register Tbsts Field Descriptions Bits Name Description Counter-Compare a Register Cmpa Field DescriptionsCounter-Compare B Register Cmpb Field Descriptions Action-Qualifier Submodule Registers Counter-Compare Control Register Cmpctl Field Descriptions CBD CBD CBU CAD CAU PRD ZROBits Name 10. Action-Qualifier Output B Control Register Aqctlb Csfb Csfa Rldcsf Otsfb Actsfb Otsfa ActsfaRldcsf Inmode Polsel Outmode Dead-Band Submodule RegistersCsfb Inmode Name Value Description PWM-Chopper Submodule Control Register16. PWM-Chopper Control Register Pcctl Bit Descriptions Reserved Chpduty Trip-Zone Submodule Control and Status RegistersPWM-Chopper Control Register Pcctl Bit Descriptions OSHT6 OSHT6 OSHT5 OSHT4 OSHT3 OSHT2 OSHT1CBC6 CBC5 CBC4 CBC3 CBC2 CBC1 CBC6 TZB 18. Trip-Zone Control Register Tzctl Field DescriptionsTZB TZA OST CBC 20. Trip-Zone Flag Register Tzflg Field Descriptions OST CBC INT 22. Trip-Zone Force Register Tzfrc Field Descriptions Event-Trigger Submodule Registers21. Trip-Zone Clear Register Tzclr Field Descriptions 23. Event-Trigger Selection Register Etsel 24. Event-Trigger Prescale Register Etps Field Descriptions Name Description 24. Event-Trigger Prescale Register Etps Field Descriptions Socb Soca Socb 25. Event-Trigger Flag Register Etflg Field Descriptions26. Event-Trigger Clear Register Etclr Field Descriptions Proper Interrupt Initialization Procedure 27. Event-Trigger Force Register Etfrc Field Descriptions 116 Table A-1. Changes for Revision D Location Modifications, Additions, and Deletions Appendix a Important Notice