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Texas Instruments 28xxx Counter-Compare Submodule Registers, 5. Time-Base Status Register TBSTS

Models: 28xxx TMS320x28xx

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Counter-Compare Submodule Registers

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Counter-Compare Submodule Registers

Figure 4-5. Time-Base Status Register (TBSTS)

15				8
	Reserved
	R-0
7	3	2	1	0
Reserved		CTRMAX	SYNCI	CTRDIR
R-0		R/W1C-0	R/W1C-0	R-1
LEGEND: R/W = Read/Write; R = Read only; R/W1C = Read/Write 1 to clear; -n = value after reset

Table 4-5. Time-Base Status Register (TBSTS) Field Descriptions

Bit	Field	Value	Description
15:3	Reserved		Reserved
2	CTRMAX		Time-Base Counter Max Latched Status Bit
		0	Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will
			have no effect.
		1	Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF. Writing
			a 1 to this bit will clear the latched event.
1	SYNCI		Input Synchronization Latched Status Bit
		0	Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has
			occurred.
		1	Reading a 1 on this bit indicates that an external synchronization event has occurred
			(EPWMxSYNCI). Writing a 1 to this bit will clear the latched event.
0	CTRDIR		Time-Base Counter Direction Status Bit. At reset, the counter is frozen; therefore, this bit has no
			meaning. To make this bit meaningful, you must first set the appropriate mode via
			TBCTL[CTRMODE].
		0	Time-Base Counter is currently counting down.
		1	Time-Base Counter is currently counting up.

4.2Counter-Compare Submodule Registers

Figure 4-6through Figure 4-8and Table 4-6through Table 4-8illustrate the counter-compare submodule control and status registers.

Figure 4-6. Counter-Compare A Register (CMPA)

15

0

CMPA

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

SPRU791D–November 2004–Revised October 2007	Registers	97
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Texas Instruments 28xxx, TMS320x28xx manual Counter-Compare Submodule Registers, 5. Time-Base Status Register TBSTS

Contents

TMS320x28xx, 28xxx Enhanced Pulse Width Modulator ePWM Module Reference GuideSubmit Documentation Feedback SPRU791D-November 2004-Revised OctoberContents Controlling Multiple Half H-Bridge HHB Converters List of Figures List of FiguresEvent-Trigger SOCB Pulse Generator List of Tables Submit Documentation Feedback SPRU791D-November 2004-Revised OctoberPreface Read This FirstRelated Documentation From Texas Instruments Data ManualsApplication Reports Tools GuidesRelated Documentation From Texas Instruments TMS320C28x, C28x are trademarks of Texas Instruments TrademarksSubmit Documentation Feedback SPRU791D-November 2004-Revised OctoberChapter IntroductionIntroduction Submodule Overview1.2 Submodule Overview 1.1 IntroductionSubmodule Overview Figure 1-1. Multiple ePWM Modules∙ PWM output signals EPWMxA and EPWMxB Figure 1-2. Submodules and Signal Connections for an ePWM Module∙ Trip-zone signals TZ1 to TZ6 ∙ ADC start-of-conversion signals EPWMxSOCA and EPWMxSOCBRegister Mapping 1.3 Register MappingOffset Register MappingSubmit Documentation Feedback Overview ePWM SubmodulesTime-Base TB Submodule Counter-Compare CC Submodule2.1 Overview Table 2-1. Submodule Configuration ParametersOverview Submit Documentation FeedbackExample 2-1. Constant Definitions Used in the Code Examples Table 2-1. Submodule Configuration Parameters continuedOverview Submit Documentation FeedbackOverview Example 2-1. Constant Definitions Used in the Code Examples continuedSubmit Documentation Feedback 2.2 Time-Base TB Submodule Figure 2-1. Time-Base Submodule Block Diagram2.2.1 Purpose of the Time-Base Submodule 2.2.2 Controlling and Monitoring the Time-base Submodule Figure 2-2. Time-Base Submodule Signals and RegistersTable 2-2. Time-Base Submodule Registers 2.2.3 Calculating PWM Period and Frequency Table 2-3. Key Time-Base Signals∙ Up-Down-Count Mode ∙ Up-Count Mode2.2.3.1 Time-Base Period Shadow Register Figure 2-3. Time-Base Frequency and Period∙ Active Register ∙ Shadow RegisterFigure 2-4. Time-Base Counter Synchronization Scheme 2.2.3.2 Time-Base Counter SynchronizationFigure 2-5. Time-Base Counter Synchronization Scheme ∙ EPWMxSYNCI Synchronization Input Pulse Figure 2-6. Time-Base Counter Synchronization Scheme∙ Software Forced Synchronization Pulse 2.2.5 Time-base Counter Modes and Timing Waveforms 2.2.4 Phase Locking the Time-Base Clocks of Multiple ePWM ModulesFigure 2-7. Time-Base Up-Count Mode Waveforms Event Figure 2-8. Time-Base Down-Count Mode WaveformsTime-Base TB Submodule Event 2.3 Counter-Compare CC SubmoduleFigure 2-11 illustrates the counter-compare submodule within the ePWM Figure 2-11. Counter-Compare Submodule2.3.2 Controlling and Monitoring the Counter-Compare Submodule 2.3.1 Purpose of the Counter-Compare SubmoduleTable 2-4. Counter-Compare Submodule Registers Figure 2-12. Detailed View of the Counter-Compare Submodule2.3.3 Operational Highlights for the Counter-Compare Submodule Table 2-5. Counter-Compare Submodule Key Signals2.3.4 Count Mode Timing Waveforms ∙ Shadow ModeFigure 2-13. Counter-Compare Event Waveforms in Up-Count Mode ∙ Up-down-count mode used to generate a symmetrical PWM waveformFigure 2-14. Counter-Compare Events in Down-Count Mode Counter-Compare CC SubmoduleSynchronization Event Synchronization Event2.4.1 Purpose of the Action-Qualifier Submodule 2.4 Action-Qualifier AQ SubmoduleFigure 2-17. Action-Qualifier Submodule Table 2-6. Action-Qualifier Submodule RegistersTable 2-7. Action-Qualifier Submodule Possible Input Events Figure 2-18. Action-Qualifier Submodule Inputs and Outputs∙ Set High ∙ Clear LowPage Table 2-8. Action-Qualifier Event Priority for Up-Down-Count Mode 2.4.3 Action-Qualifier Event PriorityTable 2-9. Action-Qualifier Event Priority for Up-Count Mode Table 2-10. Action-Qualifier Event Priority for Down-Count ModeWhen using up-count mode to generate an asymmetric PWM 2.4.4 Waveforms for Common ConfigurationsSee the Using Enhanced Pulse Width Modulator ePWM Module for 0-100% Table 2-11. Behavior if CMPA/CMPB is Greater than the PeriodFigure 2-20. Up-Down-Count Mode Symmetrical Waveform Example 2-2. Code Sample for Figure EPWMxB-Active HighAction-Qualifier AQ Submodule Action-Qualifier AQ Submodule EPWMxB-Active LowEPWMxA Example 2-3. Code Sample for FigureAction-Qualifier AQ Submodule Submit Documentation FeedbackAction-Qualifier AQ Submodule Example 2-4. Code Sample for FigureSubmit Documentation Feedback Example 2-5. Code Sample for Figure EPWMxA and EPWMxB - Active LowAction-Qualifier AQ Submodule Example 2-6. Code Sample for Figure EPWMxA and EPWMxB - ComplementaryAction-Qualifier AQ Submodule Example 2-7. Code Sample for Figure EPWMxA-Active LowAction-Qualifier AQ Submodule Submit Documentation Feedback2.5.1 Purpose of the Dead-Band Submodule 2.5 Dead-Band Generator DB Submodule2.5.2 Controlling and Monitoring the Dead-Band Submodule Figure 2-27. DeadBand Submodule∙ Mode 2-5 Classical Dead-Band Polarity Settings Figure 2-28. Configuration Options for the Dead-Band Submodule2.5.3 Operational Highlights for the Dead-Band Submodule ∙ Input Source SelectionTable 2-13. Classical Dead-Band Operating Modes action-qualifier submodule to generate the signal as shown for EPWMxADead-Band Generator DB Submodule Submit Documentation FeedbackFigure 2-29. Dead-Band Waveforms for Typical Cases 0% Duty 100% Figure 2-29 shows waveforms for typical cases where 0% duty 100%Dead-Band Generator DB Submodule Submit Documentation FeedbackFED = DBFED × TTBCLK RED = DBRED × TTBCLK 2.6.1 Purpose of the PWM-Chopper Submodule 2.6 PWM-Chopper PC Submodule2.6.2 Controlling the PWM-Chopper Submodule 2.6.3 Operational Highlights for the PWM-Chopper SubmoduleFigure 2-31. PWM-Chopper Submodule Operational Details 2.6.4 WaveformsPWM-Chopper PC Submodule Pulses 2.6.4.1 One-Shot PulseTable 2-16. Possible Pulse Width Values for SYSCLKOUT = 100 MHz Start OSHT pulse EPWMxA in PSCLK Prog. pulse width OSHTWTH OSHTSustaining Pulses 2.6.4.2 Duty Cycle Control87.5% PSCLK Period2.7.1 Purpose of the Trip-Zone Submodule 2.7 Trip-Zone TZ SubmoduleFigure 2-35. Trip-Zone Submodule 2.7.3 Operational Highlights for the Trip-Zone Submodule 2.7.2 Controlling and Monitoring the Trip-Zone SubmoduleTable 2-17. Trip-Zone Submodule Registers ∙ Cycle-by-Cycle CBCTable 2-18. Possible Actions On a Trip Event Example 2-8. Trip-Zone ConfigurationsScenario A Scenario BFigure 2-36. Trip-Zone Submodule Mode Control Logic 2.7.4 Generating Trip Event InterruptsTrip-Zone TZ Submodule Figure 2-37. Trip-Zone Submodule Interrupt Logic 2.8 Event-Trigger ET SubmoduleFigure 2-38. Event-Trigger Submodule 2.8.1 Operational Overview of the Event-Trigger Submodule SignalsTable 2-19. Event-Trigger Submodule Registers input = Figure 2-41. Event-Trigger Interrupt GeneratorFigure 2-43. Event-Trigger SOCB Pulse Generator Figure 2-42. Event-Trigger SOCA Pulse GeneratorEvent-Trigger ET Submodule Submit Documentation FeedbackSubmit Documentation Feedback SPRU791D-November 2004-Revised OctoberKey Configuration Capabilities Applications to Power TopologiesOverview of Multiple Modules Frequencies3.1 Overview of Multiple Modules 3.2 Key Configuration CapabilitiesFigure 3-1. Simplified ePWM Module Controlling Multiple Buck Converters With Independent Frequencies 3.3 Controlling Multiple Buck Converters With Independent FrequenciesSubmit Documentation Feedback Controlling Multiple Buck Converters With Independent FrequenciesIndicates this event triggers an ADC start Controlling Multiple Buck Converters With Independent FrequenciesControlling Multiple Buck Converters With Independent Frequencies Example 3-1. Configuration for Example in FigureSubmit Documentation Feedback Figure 3-5. Control of Four Buck Stages. Note FPWM2 = N x FPWM1 3.4 Controlling Multiple Buck Converters With Same FrequenciesControlling Multiple Buck Converters With Same Frequencies Figure 3-6. Buck Waveforms for Figure 3-5 Note FPWM2 = FPWM1Controlling Multiple Buck Converters With Same Frequencies Example 3-2. Code Snippet for Configuration in FigureSubmit Documentation Feedback Figure 3-7. Control of Two Half-H Bridge Stages FPWM2 = N x FPWM1 3.5 Controlling Multiple Half H-Bridge HHB ConvertersControlling Multiple Half H-Bridge HHB Converters Example 3-3. Code Snippet for Configuration in Figure 3.6 Controlling Dual 3-Phase Inverters for Motors ACI and PMSMSubmit Documentation Feedback Controlling Dual 3-Phase Inverters for Motors ACI and PMSMControlling Dual 3-Phase Inverters for Motors ACI and PMSM Controlling Dual 3-Phase Inverters for Motors ACI and PMSM Example 3-4. Code Snippet for Configuration in FigureSubmit Documentation Feedback Figure 3-11. Configuring Two PWM Modules for Phase Control 3.7 Practical Applications Using Phase Control Between PWM Modules3.8 Controlling a 3-Phase Interleaved DC/DC Converter Controlling a 3-Phase Interleaved DC/DC Converter Figure 3-13. Control of a 3-Phase Interleaved DC/DC Converter=240 Controlling a 3-Phase Interleaved DC/DC Converter Figure 3-14. 3-Phase Interleaved DC/DC Converter Waveforms for FigureControlling a 3-Phase Interleaved DC/DC Converter Example 3-5. Code Snippet for Configuration in FigureSubmit Documentation Feedback Figure 3-15. Controlling a Full-H Bridge Stage FPWM2 = FPWM1 3.9 Controlling Zero Voltage Switched Full Bridge ZVSFB ConverterFigure 3-16. ZVS Full-H Bridge Waveforms Controlling Zero Voltage Switched Full Bridge ZVSFB ConverterControlling Zero Voltage Switched Full Bridge ZVSFB Converter Example 3-6. Code Snippet for Configuration in FigureSubmit Documentation Feedback Submit Documentation Feedback SPRU791D-November 2004-Revised OctoberTime-Base Submodule Registers RegistersCounter-Compare Submodule Registers Action-Qualifier Submodule RegistersTable 4-2. Time-Base Phase Register TBPHS Field Descriptions Figure 4-2. Time-Base Phase Register TBPHS4.1 Time-Base Submodule Registers Figure 4-1. Time-Base Period Register TBPRDTable 4-4. Time-Base Control Register TBCTL Field Descriptions Figure 4-4. Time-Base Control Register TBCTLTime-Base Submodule Registers Submit Documentation FeedbackSubmit Documentation Feedback Time-Base Submodule RegistersFigure 4-5. Time-Base Status Register TBSTS 4.2 Counter-Compare Submodule RegistersTable 4-5. Time-Base Status Register TBSTS Field Descriptions Figure 4-6. Counter-Compare A Register CMPAFigure 4-7. Counter-Compare B Register CMPB Table 4-6. Counter-Compare A Register CMPA Field DescriptionsTable 4-7. Counter-Compare B Register CMPB Field Descriptions Counter-Compare Submodule RegistersFigure 4-8. Counter-Compare Control Register CMPCTL 4.3 Action-Qualifier Submodule RegistersTable 4-8. Counter-Compare Control Register CMPCTL Field Descriptions Action-Qualifier Submodule RegistersAction-Qualifier Submodule Registers Figure 4-9. Action-Qualifier Output A Control Register AQCTLASubmit Documentation Feedback Action-Qualifier Submodule Registers Figure 4-10. Action-Qualifier Output B Control Register AQCTLBSubmit Documentation Feedback Figure 4-11. Action-Qualifier Software Force Register AQSFRC Figure 4-13. Dead-Band Generator Control Register DBCTL 4.4 Dead-Band Submodule RegistersDead-Band Submodule Registers Submit Documentation FeedbackSubmit Documentation Feedback Dead-Band Submodule RegistersFigure 4-15. Dead-Band Generator Falling Edge Delay Register DBFED Figure 4-14. Dead-Band Generator Rising Edge Delay Register DBRED4.5 PWM-Chopper Submodule Control Register Figure 4-16. PWM-Chopper Control Register PCCTLPWM-Chopper Control Register PCCTL Bit Descriptions continued 4.6 Trip-Zone Submodule Control and Status RegistersTrip-Zone Submodule Control and Status Registers Submit Documentation FeedbackTrip-Zone Submodule Control and Status Registers Figure 4-17. Trip-Zone Select Register TZSELSubmit Documentation Feedback Figure 4-18. Trip-Zone Control Register TZCTL Figure 4-19. Trip-Zone Enable Interrupt Register TZEINTTable 4-18. Trip-Zone Control Register TZCTL Field Descriptions Trip-Zone Submodule Control and Status RegistersTable 4-20. Trip-Zone Flag Register TZFLG Field Descriptions Figure 4-20. Trip-Zone Flag Register TZFLGTrip-Zone Submodule Control and Status Registers Submit Documentation FeedbackFigure 4-21. Trip-Zone Clear Register TZCLR 4.7 Event-Trigger Submodule RegistersTable 4-21. Trip-Zone Clear Register TZCLR Field Descriptions Figure 4-22. Trip-Zone Force Register TZFRCTable 4-23. Event-Trigger Selection Register ETSEL Field Descriptions Figure 4-23. Event-Trigger Selection Register ETSELBits NameTable 4-24. Event-Trigger Prescale Register ETPS Field Descriptions Figure 4-24. Event-Trigger Prescale Register ETPSEvent-Trigger Submodule Registers Submit Documentation FeedbackName Figure 4-25. Event-Trigger Flag Register ETFLGDescription Submit Documentation FeedbackFigure 4-26. Event-Trigger Clear Register ETCLR Table 4-25. Event-Trigger Flag Register ETFLG Field DescriptionsTable 4-26. Event-Trigger Clear Register ETCLR Field Descriptions Event-Trigger Submodule RegistersProper Interrupt Initialization Procedure 4.8 Proper Interrupt Initialization ProcedureFigure 4-27. Event-Trigger Force Register ETFRC Table 4-27. Event-Trigger Force Register ETFRC Field DescriptionsSubmit Documentation Feedback SPRU791D-November 2004-Revised OctoberAppendix A Revision HistoryTable A-1. Changes for Revision D SPRU791D-November 2004-Revised OctoberAppendix A Table A-1. Changes for Revision D continuedSection Submit Documentation FeedbackIMPORTANT NOTICE power.ti.comProducts Applications