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Texas Instruments 28xxx, TMS320x28xx Controlling Dual 3-Phase Inverters for Motors ACI and PMSM

Models: 28xxx TMS320x28xx

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Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM)

Figure 3-9. Control of Dual 3-Phase Inverter Stages as Is Commonly Used in Motor Control

		Ext SyncIn
Master		(optional)
Master
Phase reg		SyncIn
	En	SyncIn
Φ=0°	En		EPWM1A
Φ=0°			EPWM1A
CTR=zero			EPWM1B
CTR=zero
CTR=CMPB
1	X	SyncOut
1		SyncOut
Slave
Phase reg		SyncIn	EPWM1A	EPWM2A	EPWM3A
	En	SyncIn
Φ=0°	En		EPWM2A	VAB
Φ=0°			EPWM2A	VAB
CTR=zero			EPWM2B		VCD
CTR=zero					VEF
CTR=CMPB					VEF
2	X	SyncOut
2		SyncOut	EPWM1B	EPWM2B	EPWM3B
					3 phase motor
Slave
Phase reg		SyncIn
	En	SyncIn
Φ=0°	En		EPWM3A
Φ=0°			EPWM3A	3 phase inverter #1
			EPWM3B	3 phase inverter #1
CTR=zero			EPWM3B
CTR=zero
CTR=CMPB
3	X	SyncOut
3		SyncOut
Slave
Phase reg		SyncIn
	En	SyncIn
Φ=0°	En		EPWM4A
Φ=0°			EPWM4A
CTR=zero			EPWM4B
CTR=zero
CTR=CMPB
4	X	SyncOut
4		SyncOut
Slave			EPWM4A	EPWM5A	EPWM6A
Slave
Phase reg		SyncIn		VAB
	En	SyncIn

Φ=0°			EPWM5A		VCD
Φ=0°			EPWM5A		VCD
CTR=zero			EPWM5B		VEF
CTR=zero
CTR=CMPB			EPWM4B	EPWM5B	EPWM6B
	X		EPWM4B	EPWM5B	EPWM6B
5	X	SyncOut			3 phase motor
					3 phase motor

Slave
Phase reg		SyncIn
	En	SyncIn
Φ=0°	En		EPWM6A	3 phase inverter #2
Φ=0°			EPWM6A
CTR=zero			EPWM6B
CTR=zero
CTR=CMPB
6	X	SyncOut
6		SyncOut

SPRU791D–November 2004–Revised October 2007

Applications to Power Topologies

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Texas Instruments 28xxx manual Controlling Dual 3-Phase Inverters for Motors ACI and PMSM, Submit Documentation Feedback

Contents

TMS320x28xx, 28xxx Enhanced Pulse Width Modulator ePWM Module Reference GuideSubmit Documentation Feedback SPRU791D-November 2004-Revised OctoberContents Controlling Multiple Half H-Bridge HHB Converters List of Figures List of FiguresEvent-Trigger SOCB Pulse Generator List of Tables Submit Documentation Feedback SPRU791D-November 2004-Revised OctoberPreface Read This FirstRelated Documentation From Texas Instruments Data ManualsTools Guides Application ReportsRelated Documentation From Texas Instruments TMS320C28x, C28x are trademarks of Texas Instruments TrademarksSubmit Documentation Feedback SPRU791D-November 2004-Revised OctoberChapter IntroductionIntroduction Submodule Overview1.2 Submodule Overview 1.1 IntroductionSubmodule Overview Figure 1-1. Multiple ePWM Modules∙ PWM output signals EPWMxA and EPWMxB Figure 1-2. Submodules and Signal Connections for an ePWM Module∙ Trip-zone signals TZ1 to TZ6 ∙ ADC start-of-conversion signals EPWMxSOCA and EPWMxSOCBRegister Mapping 1.3 Register MappingRegister Mapping OffsetSubmit Documentation Feedback Overview ePWM SubmodulesTime-Base TB Submodule Counter-Compare CC Submodule2.1 Overview Table 2-1. Submodule Configuration ParametersOverview Submit Documentation FeedbackExample 2-1. Constant Definitions Used in the Code Examples Table 2-1. Submodule Configuration Parameters continuedOverview Submit Documentation FeedbackExample 2-1. Constant Definitions Used in the Code Examples continued OverviewSubmit Documentation Feedback Figure 2-1. Time-Base Submodule Block Diagram 2.2 Time-Base TB Submodule2.2.1 Purpose of the Time-Base Submodule Figure 2-2. Time-Base Submodule Signals and Registers 2.2.2 Controlling and Monitoring the Time-base SubmoduleTable 2-2. Time-Base Submodule Registers 2.2.3 Calculating PWM Period and Frequency Table 2-3. Key Time-Base Signals∙ Up-Down-Count Mode ∙ Up-Count Mode2.2.3.1 Time-Base Period Shadow Register Figure 2-3. Time-Base Frequency and Period∙ Active Register ∙ Shadow RegisterFigure 2-4. Time-Base Counter Synchronization Scheme 2.2.3.2 Time-Base Counter SynchronizationFigure 2-5. Time-Base Counter Synchronization Scheme Figure 2-6. Time-Base Counter Synchronization Scheme ∙ EPWMxSYNCI Synchronization Input Pulse∙ Software Forced Synchronization Pulse 2.2.4 Phase Locking the Time-Base Clocks of Multiple ePWM Modules 2.2.5 Time-base Counter Modes and Timing WaveformsFigure 2-7. Time-Base Up-Count Mode Waveforms Figure 2-8. Time-Base Down-Count Mode Waveforms EventTime-Base TB Submodule Event 2.3 Counter-Compare CC SubmoduleFigure 2-11 illustrates the counter-compare submodule within the ePWM Figure 2-11. Counter-Compare Submodule2.3.2 Controlling and Monitoring the Counter-Compare Submodule 2.3.1 Purpose of the Counter-Compare SubmoduleTable 2-4. Counter-Compare Submodule Registers Figure 2-12. Detailed View of the Counter-Compare Submodule2.3.3 Operational Highlights for the Counter-Compare Submodule Table 2-5. Counter-Compare Submodule Key Signals2.3.4 Count Mode Timing Waveforms ∙ Shadow ModeFigure 2-13. Counter-Compare Event Waveforms in Up-Count Mode ∙ Up-down-count mode used to generate a symmetrical PWM waveformFigure 2-14. Counter-Compare Events in Down-Count Mode Counter-Compare CC SubmoduleSynchronization Event Synchronization Event2.4.1 Purpose of the Action-Qualifier Submodule 2.4 Action-Qualifier AQ SubmoduleFigure 2-17. Action-Qualifier Submodule Table 2-6. Action-Qualifier Submodule RegistersTable 2-7. Action-Qualifier Submodule Possible Input Events Figure 2-18. Action-Qualifier Submodule Inputs and Outputs∙ Set High ∙ Clear LowPage Table 2-8. Action-Qualifier Event Priority for Up-Down-Count Mode 2.4.3 Action-Qualifier Event PriorityTable 2-9. Action-Qualifier Event Priority for Up-Count Mode Table 2-10. Action-Qualifier Event Priority for Down-Count ModeWhen using up-count mode to generate an asymmetric PWM 2.4.4 Waveforms for Common ConfigurationsSee the Using Enhanced Pulse Width Modulator ePWM Module for 0-100% Table 2-11. Behavior if CMPA/CMPB is Greater than the PeriodFigure 2-20. Up-Down-Count Mode Symmetrical Waveform EPWMxB-Active High Example 2-2. Code Sample for FigureAction-Qualifier AQ Submodule Action-Qualifier AQ Submodule EPWMxB-Active LowEPWMxA Example 2-3. Code Sample for FigureAction-Qualifier AQ Submodule Submit Documentation FeedbackExample 2-4. Code Sample for Figure Action-Qualifier AQ SubmoduleSubmit Documentation Feedback EPWMxA and EPWMxB - Active Low Example 2-5. Code Sample for FigureAction-Qualifier AQ Submodule EPWMxA and EPWMxB - Complementary Example 2-6. Code Sample for FigureAction-Qualifier AQ Submodule Example 2-7. Code Sample for Figure EPWMxA-Active LowAction-Qualifier AQ Submodule Submit Documentation Feedback2.5.1 Purpose of the Dead-Band Submodule 2.5 Dead-Band Generator DB Submodule2.5.2 Controlling and Monitoring the Dead-Band Submodule Figure 2-27. DeadBand Submodule∙ Mode 2-5 Classical Dead-Band Polarity Settings Figure 2-28. Configuration Options for the Dead-Band Submodule2.5.3 Operational Highlights for the Dead-Band Submodule ∙ Input Source SelectionTable 2-13. Classical Dead-Band Operating Modes action-qualifier submodule to generate the signal as shown for EPWMxADead-Band Generator DB Submodule Submit Documentation FeedbackFigure 2-29. Dead-Band Waveforms for Typical Cases 0% Duty 100% Figure 2-29 shows waveforms for typical cases where 0% duty 100%Dead-Band Generator DB Submodule Submit Documentation FeedbackFED = DBFED × TTBCLK RED = DBRED × TTBCLK 2.6.1 Purpose of the PWM-Chopper Submodule 2.6 PWM-Chopper PC Submodule2.6.2 Controlling the PWM-Chopper Submodule 2.6.3 Operational Highlights for the PWM-Chopper Submodule2.6.4 Waveforms Figure 2-31. PWM-Chopper Submodule Operational DetailsPWM-Chopper PC Submodule Pulses 2.6.4.1 One-Shot PulseTable 2-16. Possible Pulse Width Values for SYSCLKOUT = 100 MHz Start OSHT pulse EPWMxA in PSCLK Prog. pulse width OSHTWTH OSHTSustaining Pulses 2.6.4.2 Duty Cycle Control87.5% PSCLK Period2.7 Trip-Zone TZ Submodule 2.7.1 Purpose of the Trip-Zone SubmoduleFigure 2-35. Trip-Zone Submodule 2.7.3 Operational Highlights for the Trip-Zone Submodule 2.7.2 Controlling and Monitoring the Trip-Zone SubmoduleTable 2-17. Trip-Zone Submodule Registers ∙ Cycle-by-Cycle CBCTable 2-18. Possible Actions On a Trip Event Example 2-8. Trip-Zone ConfigurationsScenario A Scenario B2.7.4 Generating Trip Event Interrupts Figure 2-36. Trip-Zone Submodule Mode Control LogicTrip-Zone TZ Submodule 2.8 Event-Trigger ET Submodule Figure 2-37. Trip-Zone Submodule Interrupt LogicFigure 2-38. Event-Trigger Submodule 2.8.1 Operational Overview of the Event-Trigger Submodule SignalsTable 2-19. Event-Trigger Submodule Registers input = Figure 2-41. Event-Trigger Interrupt GeneratorFigure 2-43. Event-Trigger SOCB Pulse Generator Figure 2-42. Event-Trigger SOCA Pulse GeneratorEvent-Trigger ET Submodule Submit Documentation FeedbackSubmit Documentation Feedback SPRU791D-November 2004-Revised OctoberKey Configuration Capabilities Applications to Power TopologiesOverview of Multiple Modules Frequencies3.2 Key Configuration Capabilities 3.1 Overview of Multiple ModulesFigure 3-1. Simplified ePWM Module Controlling Multiple Buck Converters With Independent Frequencies 3.3 Controlling Multiple Buck Converters With Independent FrequenciesSubmit Documentation Feedback Controlling Multiple Buck Converters With Independent FrequenciesIndicates this event triggers an ADC start Controlling Multiple Buck Converters With Independent FrequenciesExample 3-1. Configuration for Example in Figure Controlling Multiple Buck Converters With Independent FrequenciesSubmit Documentation Feedback Figure 3-5. Control of Four Buck Stages. Note FPWM2 = N x FPWM1 3.4 Controlling Multiple Buck Converters With Same FrequenciesControlling Multiple Buck Converters With Same Frequencies Figure 3-6. Buck Waveforms for Figure 3-5 Note FPWM2 = FPWM1Example 3-2. Code Snippet for Configuration in Figure Controlling Multiple Buck Converters With Same FrequenciesSubmit Documentation Feedback Figure 3-7. Control of Two Half-H Bridge Stages FPWM2 = N x FPWM1 3.5 Controlling Multiple Half H-Bridge HHB ConvertersControlling Multiple Half H-Bridge HHB Converters Example 3-3. Code Snippet for Configuration in Figure 3.6 Controlling Dual 3-Phase Inverters for Motors ACI and PMSMSubmit Documentation Feedback Controlling Dual 3-Phase Inverters for Motors ACI and PMSMControlling Dual 3-Phase Inverters for Motors ACI and PMSM Example 3-4. Code Snippet for Configuration in Figure Controlling Dual 3-Phase Inverters for Motors ACI and PMSMSubmit Documentation Feedback Figure 3-11. Configuring Two PWM Modules for Phase Control 3.7 Practical Applications Using Phase Control Between PWM Modules3.8 Controlling a 3-Phase Interleaved DC/DC Converter Figure 3-13. Control of a 3-Phase Interleaved DC/DC Converter Controlling a 3-Phase Interleaved DC/DC Converter=240 Controlling a 3-Phase Interleaved DC/DC Converter Figure 3-14. 3-Phase Interleaved DC/DC Converter Waveforms for FigureExample 3-5. Code Snippet for Configuration in Figure Controlling a 3-Phase Interleaved DC/DC ConverterSubmit Documentation Feedback Figure 3-15. Controlling a Full-H Bridge Stage FPWM2 = FPWM1 3.9 Controlling Zero Voltage Switched Full Bridge ZVSFB ConverterFigure 3-16. ZVS Full-H Bridge Waveforms Controlling Zero Voltage Switched Full Bridge ZVSFB ConverterExample 3-6. Code Snippet for Configuration in Figure Controlling Zero Voltage Switched Full Bridge ZVSFB ConverterSubmit Documentation Feedback Submit Documentation Feedback SPRU791D-November 2004-Revised OctoberTime-Base Submodule Registers RegistersCounter-Compare Submodule Registers Action-Qualifier Submodule RegistersTable 4-2. Time-Base Phase Register TBPHS Field Descriptions Figure 4-2. Time-Base Phase Register TBPHS4.1 Time-Base Submodule Registers Figure 4-1. Time-Base Period Register TBPRDTable 4-4. Time-Base Control Register TBCTL Field Descriptions Figure 4-4. Time-Base Control Register TBCTLTime-Base Submodule Registers Submit Documentation FeedbackSubmit Documentation Feedback Time-Base Submodule RegistersFigure 4-5. Time-Base Status Register TBSTS 4.2 Counter-Compare Submodule RegistersTable 4-5. Time-Base Status Register TBSTS Field Descriptions Figure 4-6. Counter-Compare A Register CMPAFigure 4-7. Counter-Compare B Register CMPB Table 4-6. Counter-Compare A Register CMPA Field DescriptionsTable 4-7. Counter-Compare B Register CMPB Field Descriptions Counter-Compare Submodule RegistersFigure 4-8. Counter-Compare Control Register CMPCTL 4.3 Action-Qualifier Submodule RegistersTable 4-8. Counter-Compare Control Register CMPCTL Field Descriptions Action-Qualifier Submodule RegistersFigure 4-9. Action-Qualifier Output A Control Register AQCTLA Action-Qualifier Submodule RegistersSubmit Documentation Feedback Figure 4-10. Action-Qualifier Output B Control Register AQCTLB Action-Qualifier Submodule RegistersSubmit Documentation Feedback Figure 4-11. Action-Qualifier Software Force Register AQSFRC Figure 4-13. Dead-Band Generator Control Register DBCTL 4.4 Dead-Band Submodule RegistersDead-Band Submodule Registers Submit Documentation FeedbackSubmit Documentation Feedback Dead-Band Submodule RegistersFigure 4-14. Dead-Band Generator Rising Edge Delay Register DBRED 4.5 PWM-Chopper Submodule Control RegisterFigure 4-15. Dead-Band Generator Falling Edge Delay Register DBFED Figure 4-16. PWM-Chopper Control Register PCCTLPWM-Chopper Control Register PCCTL Bit Descriptions continued 4.6 Trip-Zone Submodule Control and Status RegistersTrip-Zone Submodule Control and Status Registers Submit Documentation FeedbackFigure 4-17. Trip-Zone Select Register TZSEL Trip-Zone Submodule Control and Status RegistersSubmit Documentation Feedback Figure 4-18. Trip-Zone Control Register TZCTL Figure 4-19. Trip-Zone Enable Interrupt Register TZEINTTable 4-18. Trip-Zone Control Register TZCTL Field Descriptions Trip-Zone Submodule Control and Status RegistersTable 4-20. Trip-Zone Flag Register TZFLG Field Descriptions Figure 4-20. Trip-Zone Flag Register TZFLGTrip-Zone Submodule Control and Status Registers Submit Documentation FeedbackFigure 4-21. Trip-Zone Clear Register TZCLR 4.7 Event-Trigger Submodule RegistersTable 4-21. Trip-Zone Clear Register TZCLR Field Descriptions Figure 4-22. Trip-Zone Force Register TZFRCTable 4-23. Event-Trigger Selection Register ETSEL Field Descriptions Figure 4-23. Event-Trigger Selection Register ETSELBits NameTable 4-24. Event-Trigger Prescale Register ETPS Field Descriptions Figure 4-24. Event-Trigger Prescale Register ETPSEvent-Trigger Submodule Registers Submit Documentation FeedbackName Figure 4-25. Event-Trigger Flag Register ETFLGDescription Submit Documentation FeedbackFigure 4-26. Event-Trigger Clear Register ETCLR Table 4-25. Event-Trigger Flag Register ETFLG Field DescriptionsTable 4-26. Event-Trigger Clear Register ETCLR Field Descriptions Event-Trigger Submodule RegistersProper Interrupt Initialization Procedure 4.8 Proper Interrupt Initialization ProcedureFigure 4-27. Event-Trigger Force Register ETFRC Table 4-27. Event-Trigger Force Register ETFRC Field DescriptionsSubmit Documentation Feedback SPRU791D-November 2004-Revised OctoberAppendix A Revision HistoryTable A-1. Changes for Revision D SPRU791D-November 2004-Revised OctoberAppendix A Table A-1. Changes for Revision D continuedSection Submit Documentation FeedbackIMPORTANT NOTICE power.ti.comProducts Applications