Texas Instruments 28xxx manual Calculating PWM Period and Frequency, 3. Key Time-Base Signals

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Time-Base (TB) Submodule

	Table 2-3. Key Time-Base Signals
Signal	Description
EPWMxSYNCI	Time-base synchronization input.
	Input pulse used to synchronize the time-base counter with the counter of ePWM module earlier in the
	synchronization chain. An ePWM peripheral can be configured to use or ignore this signal. For the first ePWM
	module (EPWM1) this signal comes from a device pin. For subsequent ePWM modules this signal is passed
	from another ePWM peripheral. For example, EPWM2SYNCI is generated by the ePWM1 peripheral,
	EPWM3SYNCI is generated by ePWM2 and so forth. See Section 2.2.3.2 for information on the
	synchronization order of a particular device.
EPWMxSYNCO	Time-base synchronization output.
	This output pulse is used to synchronize the counter of an ePWM module later in the synchronization chain.
	The ePWM module generates this signal from one of three event sources:
	1. EPWMxSYNCI (Synchronization input pulse)
	2. CTR = Zero: The time-base counter equal to zero (TBCTR = 0x0000).
	3. CTR = CMPB: The time-base counter equal to the counter-compare B (TBCTR = CMPB) register.
CTR = PRD	Time-base counter equal to the specified period.
	This signal is generated whenever the counter value is equal to the active period register value. That is when
	TBCTR = TBPRD.
CTR = Zero	Time-base counter equal to zero
	This signal is generated whenever the counter value is zero. That is when TBCTR equals 0x0000.
CTR = CMPB	Time-base counter equal to active counter-compare B register (TBCTR = CMPB).
	This event is generated by the counter-compare submodule and used by the synchronization out logic
CTR_dir	Time-base counter direction.
	Indicates the current direction of the ePWM's time-base counter. This signal is high when the counter is
	increasing and low when it is decreasing.
CTR_max	Time-base counter equal max value. (TBCTR = 0xFFFF)
	Generated event when the TBCTR value reaches its maximum value. This signal is only used only as a status
	bit
TBCLK	Time-base clock.
	This is a prescaled version of the system clock (SYSCLKOUT) and is used by all submodules within the
	ePWM. This clock determines the rate at which time-base counter increments or decrements.

2.2.3 Calculating PWM Period and Frequency

The frequency of PWM events is controlled by the time-base period (TBPRD) register and the mode of the time-base counter. Figure 2-3shows the period (Tpwm) and frequency (Fpwm) relationships for the up-count, down-count, and up-down-count time-base counter modes when when the period is set to 4 (TBPRD = 4). The time increment for each step is defined by the time-base clock (TBCLK) which is a prescaled version of the system clock (SYSCLKOUT).

The time-base counter has three modes of operation selected by the time-base control register (TBCTL):

∙Up-Down-Count Mode:

In up-down-count mode, the time-base counter starts from zero and increments until the period (TBPRD) value is reached. When the period value is reached, the time-base counter then decrements until it reaches zero. At this point the counter repeats the pattern and begins to increment.

∙Up-Count Mode:

In this mode, the time-base counter starts from zero and increments until it reaches the value in the period register (TBPRD). When the period value is reached, the time-base counter resets to zero and begins to increment once again.

∙Down-Count Mode:

In down-count mode, the time-base counter starts from the period (TBPRD) value and decrements until it reaches zero. When it reaches zero, the time-base counter is reset to the period value and it begins to decrement once again.

SPRU791D–November 2004–Revised October 2007 ePWM Submodules 25

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