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TMS320x28xx, 28xxx manual SPRU791D-November 2004-Revised October
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28xxx
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1. Time-Base Submodule Block Diagram
1. Submodule Configuration Parameters
Proper Interrupt Initialization Procedure
14. Dead-Band Generator Rising Edge Delay Register DBRED
2. Submodules and Signal Connections for an ePWM Module
Phase Locking the Time-Base Clocks of Multiple ePWM Modules
∙ Mode 2-5 Classical Dead-Band Polarity Settings
How to
Applications to Power Topologies
19. Trip-Zone Enable Interrupt Register TZEINT
Page 12
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SPRU791D–November
2004–Revised
October 2007
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Page 11
Page 13
Page 12
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Page 11
Page 13
Contents
Reference Guide
TMS320x28xx, 28xxx Enhanced Pulse Width Modulator ePWM Module
SPRU791D-November 2004-Revised October
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Contents
Controlling Multiple Half H-Bridge HHB Converters
List of Figures
List of Figures
Event-Trigger SOCB Pulse Generator
List of Tables
SPRU791D-November 2004-Revised October
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Read This First
Preface
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Data Manuals
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Application Reports
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Trademarks
TMS320C28x, C28x are trademarks of Texas Instruments
SPRU791D-November 2004-Revised October
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Introduction
Chapter
Introduction
Submodule Overview
1.1 Introduction
1.2 Submodule Overview
Figure 1-1. Multiple ePWM Modules
Submodule Overview
Figure 1-2. Submodules and Signal Connections for an ePWM Module
∙ PWM output signals EPWMxA and EPWMxB
∙ Trip-zone signals TZ1 to TZ6
∙ ADC start-of-conversion signals EPWMxSOCA and EPWMxSOCB
1.3 Register Mapping
Register Mapping
Register Mapping
Offset
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ePWM Submodules
Overview
Time-Base TB Submodule
Counter-Compare CC Submodule
Table 2-1. Submodule Configuration Parameters
2.1 Overview
Overview
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Table 2-1. Submodule Configuration Parameters continued
Example 2-1. Constant Definitions Used in the Code Examples
Overview
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Example 2-1. Constant Definitions Used in the Code Examples continued
Overview
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Figure 2-1. Time-Base Submodule Block Diagram
2.2 Time-Base TB Submodule
2.2.1 Purpose of the Time-Base Submodule
Figure 2-2. Time-Base Submodule Signals and Registers
2.2.2 Controlling and Monitoring the Time-base Submodule
Table 2-2. Time-Base Submodule Registers
Table 2-3. Key Time-Base Signals
2.2.3 Calculating PWM Period and Frequency
∙ Up-Down-Count Mode
∙ Up-Count Mode
Figure 2-3. Time-Base Frequency and Period
2.2.3.1 Time-Base Period Shadow Register
∙ Active Register
∙ Shadow Register
2.2.3.2 Time-Base Counter Synchronization
Figure 2-4. Time-Base Counter Synchronization Scheme
Figure 2-5. Time-Base Counter Synchronization Scheme
Figure 2-6. Time-Base Counter Synchronization Scheme
∙ EPWMxSYNCI Synchronization Input Pulse
∙ Software Forced Synchronization Pulse
2.2.4 Phase Locking the Time-Base Clocks of Multiple ePWM Modules
2.2.5 Time-base Counter Modes and Timing Waveforms
Figure 2-7. Time-Base Up-Count Mode Waveforms
Figure 2-8. Time-Base Down-Count Mode Waveforms
Event
Time-Base TB Submodule
2.3 Counter-Compare CC Submodule
Event
Figure 2-11 illustrates the counter-compare submodule within the ePWM
Figure 2-11. Counter-Compare Submodule
2.3.1 Purpose of the Counter-Compare Submodule
2.3.2 Controlling and Monitoring the Counter-Compare Submodule
Table 2-4. Counter-Compare Submodule Registers
Figure 2-12. Detailed View of the Counter-Compare Submodule
Table 2-5. Counter-Compare Submodule Key Signals
2.3.3 Operational Highlights for the Counter-Compare Submodule
2.3.4 Count Mode Timing Waveforms
∙ Shadow Mode
∙ Up-down-count mode used to generate a symmetrical PWM waveform
Figure 2-13. Counter-Compare Event Waveforms in Up-Count Mode
Figure 2-14. Counter-Compare Events in Down-Count Mode
Counter-Compare CC Submodule
Synchronization Event
Synchronization Event
2.4 Action-Qualifier AQ Submodule
2.4.1 Purpose of the Action-Qualifier Submodule
Figure 2-17. Action-Qualifier Submodule
Table 2-6. Action-Qualifier Submodule Registers
Figure 2-18. Action-Qualifier Submodule Inputs and Outputs
Table 2-7. Action-Qualifier Submodule Possible Input Events
∙ Set High
∙ Clear Low
Page
2.4.3 Action-Qualifier Event Priority
Table 2-8. Action-Qualifier Event Priority for Up-Down-Count Mode
Table 2-9. Action-Qualifier Event Priority for Up-Count Mode
Table 2-10. Action-Qualifier Event Priority for Down-Count Mode
2.4.4 Waveforms for Common Configurations
When using up-count mode to generate an asymmetric PWM
See the Using Enhanced Pulse Width Modulator ePWM Module for 0-100%
Table 2-11. Behavior if CMPA/CMPB is Greater than the Period
Figure 2-20. Up-Down-Count Mode Symmetrical Waveform
EPWMxB-Active High
Example 2-2. Code Sample for Figure
Action-Qualifier AQ Submodule
EPWMxB-Active Low
Action-Qualifier AQ Submodule
Example 2-3. Code Sample for Figure
EPWMxA
Action-Qualifier AQ Submodule
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Example 2-4. Code Sample for Figure
Action-Qualifier AQ Submodule
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EPWMxA and EPWMxB - Active Low
Example 2-5. Code Sample for Figure
Action-Qualifier AQ Submodule
EPWMxA and EPWMxB - Complementary
Example 2-6. Code Sample for Figure
Action-Qualifier AQ Submodule
EPWMxA-Active Low
Example 2-7. Code Sample for Figure
Action-Qualifier AQ Submodule
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2.5 Dead-Band Generator DB Submodule
2.5.1 Purpose of the Dead-Band Submodule
2.5.2 Controlling and Monitoring the Dead-Band Submodule
Figure 2-27. DeadBand Submodule
Figure 2-28. Configuration Options for the Dead-Band Submodule
∙ Mode 2-5 Classical Dead-Band Polarity Settings
2.5.3 Operational Highlights for the Dead-Band Submodule
∙ Input Source Selection
action-qualifier submodule to generate the signal as shown for EPWMxA
Table 2-13. Classical Dead-Band Operating Modes
Dead-Band Generator DB Submodule
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Figure 2-29 shows waveforms for typical cases where 0% duty 100%
Figure 2-29. Dead-Band Waveforms for Typical Cases 0% Duty 100%
Dead-Band Generator DB Submodule
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FED = DBFED × TTBCLK RED = DBRED × TTBCLK
2.6 PWM-Chopper PC Submodule
2.6.1 Purpose of the PWM-Chopper Submodule
2.6.2 Controlling the PWM-Chopper Submodule
2.6.3 Operational Highlights for the PWM-Chopper Submodule
2.6.4 Waveforms
Figure 2-31. PWM-Chopper Submodule Operational Details
PWM-Chopper PC Submodule
2.6.4.1 One-Shot Pulse
Pulses
Table 2-16. Possible Pulse Width Values for SYSCLKOUT = 100 MHz
Start OSHT pulse EPWMxA in PSCLK Prog. pulse width OSHTWTH OSHT
2.6.4.2 Duty Cycle Control
Sustaining Pulses
87.5%
PSCLK Period
2.7 Trip-Zone TZ Submodule
2.7.1 Purpose of the Trip-Zone Submodule
Figure 2-35. Trip-Zone Submodule
2.7.2 Controlling and Monitoring the Trip-Zone Submodule
2.7.3 Operational Highlights for the Trip-Zone Submodule
Table 2-17. Trip-Zone Submodule Registers
∙ Cycle-by-Cycle CBC
Example 2-8. Trip-Zone Configurations
Table 2-18. Possible Actions On a Trip Event
Scenario A
Scenario B
2.7.4 Generating Trip Event Interrupts
Figure 2-36. Trip-Zone Submodule Mode Control Logic
Trip-Zone TZ Submodule
2.8 Event-Trigger ET Submodule
Figure 2-37. Trip-Zone Submodule Interrupt Logic
Figure 2-38. Event-Trigger Submodule
Signals
2.8.1 Operational Overview of the Event-Trigger Submodule
Table 2-19. Event-Trigger Submodule Registers
Figure 2-41. Event-Trigger Interrupt Generator
input =
Figure 2-42. Event-Trigger SOCA Pulse Generator
Figure 2-43. Event-Trigger SOCB Pulse Generator
Event-Trigger ET Submodule
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Applications to Power Topologies
Key Configuration Capabilities
Overview of Multiple Modules
Frequencies
3.2 Key Configuration Capabilities
3.1 Overview of Multiple Modules
Figure 3-1. Simplified ePWM Module
3.3 Controlling Multiple Buck Converters With Independent Frequencies
Controlling Multiple Buck Converters With Independent Frequencies
Controlling Multiple Buck Converters With Independent Frequencies
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Controlling Multiple Buck Converters With Independent Frequencies
Indicates this event triggers an ADC start
Example 3-1. Configuration for Example in Figure
Controlling Multiple Buck Converters With Independent Frequencies
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3.4 Controlling Multiple Buck Converters With Same Frequencies
Figure 3-5. Control of Four Buck Stages. Note FPWM2 = N x FPWM1
Figure 3-6. Buck Waveforms for Figure 3-5 Note FPWM2 = FPWM1
Controlling Multiple Buck Converters With Same Frequencies
Example 3-2. Code Snippet for Configuration in Figure
Controlling Multiple Buck Converters With Same Frequencies
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3.5 Controlling Multiple Half H-Bridge HHB Converters
Figure 3-7. Control of Two Half-H Bridge Stages FPWM2 = N x FPWM1
Controlling Multiple Half H-Bridge HHB Converters
3.6 Controlling Dual 3-Phase Inverters for Motors ACI and PMSM
Example 3-3. Code Snippet for Configuration in Figure
Controlling Dual 3-Phase Inverters for Motors ACI and PMSM
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Controlling Dual 3-Phase Inverters for Motors ACI and PMSM
Example 3-4. Code Snippet for Configuration in Figure
Controlling Dual 3-Phase Inverters for Motors ACI and PMSM
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3.7 Practical Applications Using Phase Control Between PWM Modules
Figure 3-11. Configuring Two PWM Modules for Phase Control
3.8 Controlling a 3-Phase Interleaved DC/DC Converter
Figure 3-13. Control of a 3-Phase Interleaved DC/DC Converter
Controlling a 3-Phase Interleaved DC/DC Converter
=240
Figure 3-14. 3-Phase Interleaved DC/DC Converter Waveforms for Figure
Controlling a 3-Phase Interleaved DC/DC Converter
Example 3-5. Code Snippet for Configuration in Figure
Controlling a 3-Phase Interleaved DC/DC Converter
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3.9 Controlling Zero Voltage Switched Full Bridge ZVSFB Converter
Figure 3-15. Controlling a Full-H Bridge Stage FPWM2 = FPWM1
Controlling Zero Voltage Switched Full Bridge ZVSFB Converter
Figure 3-16. ZVS Full-H Bridge Waveforms
Example 3-6. Code Snippet for Configuration in Figure
Controlling Zero Voltage Switched Full Bridge ZVSFB Converter
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Registers
Time-Base Submodule Registers
Counter-Compare Submodule Registers
Action-Qualifier Submodule Registers
Figure 4-2. Time-Base Phase Register TBPHS
Table 4-2. Time-Base Phase Register TBPHS Field Descriptions
4.1 Time-Base Submodule Registers
Figure 4-1. Time-Base Period Register TBPRD
Figure 4-4. Time-Base Control Register TBCTL
Table 4-4. Time-Base Control Register TBCTL Field Descriptions
Time-Base Submodule Registers
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Time-Base Submodule Registers
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4.2 Counter-Compare Submodule Registers
Figure 4-5. Time-Base Status Register TBSTS
Table 4-5. Time-Base Status Register TBSTS Field Descriptions
Figure 4-6. Counter-Compare A Register CMPA
Table 4-6. Counter-Compare A Register CMPA Field Descriptions
Figure 4-7. Counter-Compare B Register CMPB
Table 4-7. Counter-Compare B Register CMPB Field Descriptions
Counter-Compare Submodule Registers
4.3 Action-Qualifier Submodule Registers
Figure 4-8. Counter-Compare Control Register CMPCTL
Table 4-8. Counter-Compare Control Register CMPCTL Field Descriptions
Action-Qualifier Submodule Registers
Figure 4-9. Action-Qualifier Output A Control Register AQCTLA
Action-Qualifier Submodule Registers
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Figure 4-10. Action-Qualifier Output B Control Register AQCTLB
Action-Qualifier Submodule Registers
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Figure 4-11. Action-Qualifier Software Force Register AQSFRC
4.4 Dead-Band Submodule Registers
Figure 4-13. Dead-Band Generator Control Register DBCTL
Dead-Band Submodule Registers
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Dead-Band Submodule Registers
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Figure 4-14. Dead-Band Generator Rising Edge Delay Register DBRED
Figure 4-15. Dead-Band Generator Falling Edge Delay Register DBFED
4.5 PWM-Chopper Submodule Control Register
Figure 4-16. PWM-Chopper Control Register PCCTL
4.6 Trip-Zone Submodule Control and Status Registers
PWM-Chopper Control Register PCCTL Bit Descriptions continued
Trip-Zone Submodule Control and Status Registers
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Figure 4-17. Trip-Zone Select Register TZSEL
Trip-Zone Submodule Control and Status Registers
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Figure 4-19. Trip-Zone Enable Interrupt Register TZEINT
Figure 4-18. Trip-Zone Control Register TZCTL
Table 4-18. Trip-Zone Control Register TZCTL Field Descriptions
Trip-Zone Submodule Control and Status Registers
Figure 4-20. Trip-Zone Flag Register TZFLG
Table 4-20. Trip-Zone Flag Register TZFLG Field Descriptions
Trip-Zone Submodule Control and Status Registers
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4.7 Event-Trigger Submodule Registers
Figure 4-21. Trip-Zone Clear Register TZCLR
Table 4-21. Trip-Zone Clear Register TZCLR Field Descriptions
Figure 4-22. Trip-Zone Force Register TZFRC
Figure 4-23. Event-Trigger Selection Register ETSEL
Table 4-23. Event-Trigger Selection Register ETSEL Field Descriptions
Bits
Name
Figure 4-24. Event-Trigger Prescale Register ETPS
Table 4-24. Event-Trigger Prescale Register ETPS Field Descriptions
Event-Trigger Submodule Registers
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Figure 4-25. Event-Trigger Flag Register ETFLG
Name
Description
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Table 4-25. Event-Trigger Flag Register ETFLG Field Descriptions
Figure 4-26. Event-Trigger Clear Register ETCLR
Table 4-26. Event-Trigger Clear Register ETCLR Field Descriptions
Event-Trigger Submodule Registers
4.8 Proper Interrupt Initialization Procedure
Proper Interrupt Initialization Procedure
Figure 4-27. Event-Trigger Force Register ETFRC
Table 4-27. Event-Trigger Force Register ETFRC Field Descriptions
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Revision History
Appendix A
Table A-1. Changes for Revision D
SPRU791D-November 2004-Revised October
Table A-1. Changes for Revision D continued
Appendix A
Section
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