Texas Instruments 28xxx, TMS320x28xx manual Waveforms for Common Configurations

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Action-Qualifier (AQ) Submodule

Table 2-11. Behavior if CMPA/CMPB is Greater than the Period

Counter Mode	Compare on Up-Count Event
	CAU/CBU
Up-Count Mode	If CMPA/CMPB ≤ TBPRD period, then the event
	occurs on a compare match (TBCTR=CMPA or
	CMPB).
	If CMPA/CMPB > TBPRD, then the event will not
	occur.
Down-Count Mode	Never occurs.
Up-Down-Count	If CMPA/CMPB < TBPRD and the counter is
Mode	incrementing, the event occurs on a compare match
	(TBCTR=CMPA or CMPB).
	If CMPA/CMPB is ≥ TBPRD, the event will occur on a
	period match (TBCTR = TBPRD).

Compare on Down-Count Event

CAU/CBU

Never occurs.

If CMPA/CMPB < TBPRD, the event will occur on a compare match (TBCTR=CMPA or CMPB).

If CMPA/CMPB ≥ TBPRD, the event will occur on a period match (TBCTR=TBPRD).

If CMPA/CMPB < TBPRD and the counter is decrementing, the event occurs on a compare match (TBCTR=CMPA or CMPB).

If CMPA/CMPB ≥ TBPRD, the event occurs on a period match (TBCTR=TBPRD).

2.4.4 Waveforms for Common Configurations

Note: The waveforms in this document show the ePWMs behavior for a static compare register value. In a running system, the active compare registers (CMPA and CMPB) are typically updated from their respective shadow registers once every period. The user specifies when the update will take place; either when the time-base counter reaches zero or when the time-base counter reaches period. There are some cases when the action based on the new value can be delayed by one period or the action based on the old value can take effect for an extra period. Some PWM configurations avoid this situation. These include, but are not limited to, the following:

Use up-down-count mode to generate a symmetric PWM:

∙If you load CMPA/CMPB on zero, then use CMPA/CMPB values greater than or equal to 1.

∙If you load CMPA/CMPB on period, then use CMPA/CMPB values less than or equal to TBPRD-1.

This means there will always be a pulse of at least one TBCLK cycle in a

PWM period which, when very short, tend to be ignored by the system.

Use up-down-count mode to generate an asymmetric PWM:

∙To achieve 50%-0% asymmetric PWM use the following configuration: Load CMPA/CMPB on period and use the period action to clear the PWM and a compare-up action to set the PWM. Modulate the compare value from 0 to TBPRD to achieve 50%-0% PWM duty.

When using up-count mode to generate an asymmetric PWM:

∙To achieve 0-100% asymmetric PWM use the following configuration: Load CMPA/CMPB on TBPRD. Use the Zero action to set the PWM and a compare-up action to clear the PWM. Modulate the compare value from 0 to TBPRD+1 to achieve 0-100% PWM duty.

See the Using Enhanced Pulse Width Modulator (ePWM) Module for 0-100%

Duty Cycle Control Application Report (literature number SPRAAI1)

Figure 2-20shows how a symmetric PWM waveform can be generated using the up-down-count mode of the TBCTR. In this mode 0%-100% DC modulation is achieved by using equal compare matches on the up count and down count portions of the waveform. In the example shown, CMPA is used to make the comparison. When the counter is incrementing the CMPA match will pull the PWM output high. Likewise, when the counter is decrementing the compare match will pull the PWM signal low. When CMPA = 0, the PWM signal is low for the entire period giving the 0% duty waveform. When CMPA = TBPRD, the PWM signal is high achieving 100% duty.

SPRU791D–November 2004–Revised October 2007 ePWM Submodules 41

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