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Texas Instruments TMS320x28xx, 28xxx manual Introduction, Submodule Overview

Models: 28xxx TMS320x28xx

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1.1Introduction

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Introduction

1.1Introduction

An effective PWM peripheral must be able to generate complex pulse width waveforms with minimal CPU overhead or intervention. It needs to be highly programmable and very flexible while being easy to understand and use. The ePWM unit described here addresses these requirements by allocating all needed timing and control resources on a per PWM channel basis. Cross coupling or sharing of resources has been avoided; instead, the ePWM is built up from smaller single channel modules with separate resources and that can operate together as required to form a system. This modular approach results in an orthogonal architecture and provides a more transparent view of the peripheral structure, helping users to understand its operation quickly.

In this document the letter x within a signal or module name is used to indicate a generic ePWM instance on a device. For example output signals EPWMxA and EPWMxB refer to the output signals from the ePWMx instance. Thus, EPWM1A and EPWM1B belong to ePWM1 and likewise EPWM4A and EPWM4B belong to ePWM4.

1.2Submodule Overview

The ePWM module represents one complete PWM channel composed of two PWM outputs: EPWMxA and EPWMxB. Multiple ePWM modules are instanced within a device as shown in Figure 1-1. Each ePWM instance is identical with one exception. Some instances include a hardware extension that allows more precise control of the PWM outputs. This extension is the high-resolution pulse width modulator (HRPWM) and is described in the TMS320x28xx, 28xxx High-Resolution Pulse Width Modulator

(HRPWM) Reference Guide (SPRU924). See the device-specific data manual to determine which ePWM instances include this feature. Each ePWM module is indicated by a numerical value starting with 1. For example ePWM1 is the first instance and ePWM3 is the 3rd instance in the system and ePWMx indicates any instance.

The ePWM modules are chained together via a clock synchronization scheme that allows them to operate as a single system when required. Additionally, this synchronization scheme can be extended to the capture peripheral modules (eCAP). The number of modules is device-dependent and based on target application needs. Modules can also operate stand-alone.

Each ePWM module supports the following features:

∙Dedicated 16-bit time-base counter with period and frequency control

∙Two PWM outputs (EPWMxA and EPWMxB) that can be used in the following configurations::

–Two independent PWM outputs with single-edge operation

–Two independent PWM outputs with dual-edge symmetric operation

–One independent PWM output with dual-edge asymmetric operation

∙Asynchronous override control of PWM signals through software.

∙Programmable phase-control support for lag or lead operation relative to other ePWM modules.

∙Hardware-locked (synchronized) phase relationship on a cycle-by-cycle basis.

∙Dead-band generation with independent rising and falling edge delay control.

∙Programmable trip zone allocation of both cycle-by-cycle trip and one-shot trip on fault conditions.

∙A trip condition can force either high, low, or high-impedance state logic levels at PWM outputs.

∙All events can trigger both CPU interrupts and ADC start of conversion (SOC)

∙Programmable event prescaling minimizes CPU overhead on interrupts.

∙PWM chopping by high-frequency carrier signal, useful for pulse transformer gate drives.

Each ePWM module is connected to the input/output signals shown in Figure 1-1. The signals are described in detail in subsequent sections.

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Introduction

SPRU791D–November 2004–Revised October 2007

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Texas Instruments TMS320x28xx, 28xxx manual Introduction, Submodule Overview

Contents

Reference Guide TMS320x28xx, 28xxx Enhanced Pulse Width Modulator ePWM ModuleSPRU791D-November 2004-Revised October Submit Documentation FeedbackContents Controlling Multiple Half H-Bridge HHB Converters List of Figures List of FiguresEvent-Trigger SOCB Pulse Generator List of Tables SPRU791D-November 2004-Revised October Submit Documentation FeedbackRelated Documentation From Texas Instruments Read This FirstPreface Data ManualsRelated Documentation From Texas Instruments Tools GuidesApplication Reports Trademarks TMS320C28x, C28x are trademarks of Texas InstrumentsSPRU791D-November 2004-Revised October Submit Documentation FeedbackIntroduction IntroductionChapter Submodule Overview1.1 Introduction 1.2 Submodule OverviewFigure 1-1. Multiple ePWM Modules Submodule Overview∙ Trip-zone signals TZ1 to TZ6 Figure 1-2. Submodules and Signal Connections for an ePWM Module∙ PWM output signals EPWMxA and EPWMxB ∙ ADC start-of-conversion signals EPWMxSOCA and EPWMxSOCB1.3 Register Mapping Register MappingSubmit Documentation Feedback Register MappingOffset Time-Base TB Submodule ePWM SubmodulesOverview Counter-Compare CC SubmoduleOverview Table 2-1. Submodule Configuration Parameters2.1 Overview Submit Documentation FeedbackOverview Table 2-1. Submodule Configuration Parameters continuedExample 2-1. Constant Definitions Used in the Code Examples Submit Documentation FeedbackSubmit Documentation Feedback Example 2-1. Constant Definitions Used in the Code Examples continuedOverview 2.2.1 Purpose of the Time-Base Submodule Figure 2-1. Time-Base Submodule Block Diagram2.2 Time-Base TB Submodule Table 2-2. Time-Base Submodule Registers Figure 2-2. Time-Base Submodule Signals and Registers2.2.2 Controlling and Monitoring the Time-base Submodule ∙ Up-Down-Count Mode Table 2-3. Key Time-Base Signals2.2.3 Calculating PWM Period and Frequency ∙ Up-Count Mode∙ Active Register Figure 2-3. Time-Base Frequency and Period2.2.3.1 Time-Base Period Shadow Register ∙ Shadow Register2.2.3.2 Time-Base Counter Synchronization Figure 2-4. Time-Base Counter Synchronization SchemeFigure 2-5. Time-Base Counter Synchronization Scheme ∙ Software Forced Synchronization Pulse Figure 2-6. Time-Base Counter Synchronization Scheme∙ EPWMxSYNCI Synchronization Input Pulse Figure 2-7. Time-Base Up-Count Mode Waveforms 2.2.4 Phase Locking the Time-Base Clocks of Multiple ePWM Modules2.2.5 Time-base Counter Modes and Timing Waveforms Time-Base TB Submodule Figure 2-8. Time-Base Down-Count Mode WaveformsEvent Figure 2-11 illustrates the counter-compare submodule within the ePWM 2.3 Counter-Compare CC SubmoduleEvent Figure 2-11. Counter-Compare SubmoduleTable 2-4. Counter-Compare Submodule Registers 2.3.1 Purpose of the Counter-Compare Submodule2.3.2 Controlling and Monitoring the Counter-Compare Submodule Figure 2-12. Detailed View of the Counter-Compare Submodule2.3.4 Count Mode Timing Waveforms Table 2-5. Counter-Compare Submodule Key Signals2.3.3 Operational Highlights for the Counter-Compare Submodule ∙ Shadow ModeFigure 2-14. Counter-Compare Events in Down-Count Mode ∙ Up-down-count mode used to generate a symmetrical PWM waveformFigure 2-13. Counter-Compare Event Waveforms in Up-Count Mode Counter-Compare CC SubmoduleSynchronization Event Synchronization EventFigure 2-17. Action-Qualifier Submodule 2.4 Action-Qualifier AQ Submodule2.4.1 Purpose of the Action-Qualifier Submodule Table 2-6. Action-Qualifier Submodule Registers∙ Set High Figure 2-18. Action-Qualifier Submodule Inputs and OutputsTable 2-7. Action-Qualifier Submodule Possible Input Events ∙ Clear LowPage Table 2-9. Action-Qualifier Event Priority for Up-Count Mode 2.4.3 Action-Qualifier Event PriorityTable 2-8. Action-Qualifier Event Priority for Up-Down-Count Mode Table 2-10. Action-Qualifier Event Priority for Down-Count ModeSee the Using Enhanced Pulse Width Modulator ePWM Module for 0-100% 2.4.4 Waveforms for Common ConfigurationsWhen using up-count mode to generate an asymmetric PWM Table 2-11. Behavior if CMPA/CMPB is Greater than the PeriodFigure 2-20. Up-Down-Count Mode Symmetrical Waveform Action-Qualifier AQ Submodule EPWMxB-Active HighExample 2-2. Code Sample for Figure EPWMxB-Active Low Action-Qualifier AQ SubmoduleAction-Qualifier AQ Submodule Example 2-3. Code Sample for FigureEPWMxA Submit Documentation FeedbackSubmit Documentation Feedback Example 2-4. Code Sample for FigureAction-Qualifier AQ Submodule Action-Qualifier AQ Submodule EPWMxA and EPWMxB - Active LowExample 2-5. Code Sample for Figure Action-Qualifier AQ Submodule EPWMxA and EPWMxB - ComplementaryExample 2-6. Code Sample for Figure Action-Qualifier AQ Submodule EPWMxA-Active LowExample 2-7. Code Sample for Figure Submit Documentation Feedback2.5.2 Controlling and Monitoring the Dead-Band Submodule 2.5 Dead-Band Generator DB Submodule2.5.1 Purpose of the Dead-Band Submodule Figure 2-27. DeadBand Submodule2.5.3 Operational Highlights for the Dead-Band Submodule Figure 2-28. Configuration Options for the Dead-Band Submodule∙ Mode 2-5 Classical Dead-Band Polarity Settings ∙ Input Source SelectionDead-Band Generator DB Submodule action-qualifier submodule to generate the signal as shown for EPWMxATable 2-13. Classical Dead-Band Operating Modes Submit Documentation FeedbackDead-Band Generator DB Submodule Figure 2-29 shows waveforms for typical cases where 0% duty 100%Figure 2-29. Dead-Band Waveforms for Typical Cases 0% Duty 100% Submit Documentation FeedbackFED = DBFED × TTBCLK RED = DBRED × TTBCLK 2.6.2 Controlling the PWM-Chopper Submodule 2.6 PWM-Chopper PC Submodule2.6.1 Purpose of the PWM-Chopper Submodule 2.6.3 Operational Highlights for the PWM-Chopper SubmodulePWM-Chopper PC Submodule 2.6.4 WaveformsFigure 2-31. PWM-Chopper Submodule Operational Details Table 2-16. Possible Pulse Width Values for SYSCLKOUT = 100 MHz 2.6.4.1 One-Shot PulsePulses Start OSHT pulse EPWMxA in PSCLK Prog. pulse width OSHTWTH OSHT87.5% 2.6.4.2 Duty Cycle ControlSustaining Pulses PSCLK PeriodFigure 2-35. Trip-Zone Submodule 2.7 Trip-Zone TZ Submodule2.7.1 Purpose of the Trip-Zone Submodule Table 2-17. Trip-Zone Submodule Registers 2.7.2 Controlling and Monitoring the Trip-Zone Submodule2.7.3 Operational Highlights for the Trip-Zone Submodule ∙ Cycle-by-Cycle CBCScenario A Example 2-8. Trip-Zone ConfigurationsTable 2-18. Possible Actions On a Trip Event Scenario BTrip-Zone TZ Submodule 2.7.4 Generating Trip Event InterruptsFigure 2-36. Trip-Zone Submodule Mode Control Logic Figure 2-38. Event-Trigger Submodule 2.8 Event-Trigger ET SubmoduleFigure 2-37. Trip-Zone Submodule Interrupt Logic Signals 2.8.1 Operational Overview of the Event-Trigger SubmoduleTable 2-19. Event-Trigger Submodule Registers Figure 2-41. Event-Trigger Interrupt Generator input =Event-Trigger ET Submodule Figure 2-42. Event-Trigger SOCA Pulse GeneratorFigure 2-43. Event-Trigger SOCB Pulse Generator Submit Documentation FeedbackSPRU791D-November 2004-Revised October Submit Documentation FeedbackOverview of Multiple Modules Applications to Power TopologiesKey Configuration Capabilities FrequenciesFigure 3-1. Simplified ePWM Module 3.2 Key Configuration Capabilities3.1 Overview of Multiple Modules 3.3 Controlling Multiple Buck Converters With Independent Frequencies Controlling Multiple Buck Converters With Independent FrequenciesControlling Multiple Buck Converters With Independent Frequencies Submit Documentation FeedbackControlling Multiple Buck Converters With Independent Frequencies Indicates this event triggers an ADC startSubmit Documentation Feedback Example 3-1. Configuration for Example in FigureControlling Multiple Buck Converters With Independent Frequencies 3.4 Controlling Multiple Buck Converters With Same Frequencies Figure 3-5. Control of Four Buck Stages. Note FPWM2 = N x FPWM1Figure 3-6. Buck Waveforms for Figure 3-5 Note FPWM2 = FPWM1 Controlling Multiple Buck Converters With Same FrequenciesSubmit Documentation Feedback Example 3-2. Code Snippet for Configuration in FigureControlling Multiple Buck Converters With Same Frequencies 3.5 Controlling Multiple Half H-Bridge HHB Converters Figure 3-7. Control of Two Half-H Bridge Stages FPWM2 = N x FPWM1Controlling Multiple Half H-Bridge HHB Converters 3.6 Controlling Dual 3-Phase Inverters for Motors ACI and PMSM Example 3-3. Code Snippet for Configuration in FigureControlling Dual 3-Phase Inverters for Motors ACI and PMSM Submit Documentation FeedbackControlling Dual 3-Phase Inverters for Motors ACI and PMSM Submit Documentation Feedback Example 3-4. Code Snippet for Configuration in FigureControlling Dual 3-Phase Inverters for Motors ACI and PMSM 3.7 Practical Applications Using Phase Control Between PWM Modules Figure 3-11. Configuring Two PWM Modules for Phase Control3.8 Controlling a 3-Phase Interleaved DC/DC Converter =240 Figure 3-13. Control of a 3-Phase Interleaved DC/DC ConverterControlling a 3-Phase Interleaved DC/DC Converter Figure 3-14. 3-Phase Interleaved DC/DC Converter Waveforms for Figure Controlling a 3-Phase Interleaved DC/DC ConverterSubmit Documentation Feedback Example 3-5. Code Snippet for Configuration in FigureControlling a 3-Phase Interleaved DC/DC Converter 3.9 Controlling Zero Voltage Switched Full Bridge ZVSFB Converter Figure 3-15. Controlling a Full-H Bridge Stage FPWM2 = FPWM1Controlling Zero Voltage Switched Full Bridge ZVSFB Converter Figure 3-16. ZVS Full-H Bridge WaveformsSubmit Documentation Feedback Example 3-6. Code Snippet for Configuration in FigureControlling Zero Voltage Switched Full Bridge ZVSFB Converter SPRU791D-November 2004-Revised October Submit Documentation FeedbackCounter-Compare Submodule Registers RegistersTime-Base Submodule Registers Action-Qualifier Submodule Registers4.1 Time-Base Submodule Registers Figure 4-2. Time-Base Phase Register TBPHSTable 4-2. Time-Base Phase Register TBPHS Field Descriptions Figure 4-1. Time-Base Period Register TBPRDTime-Base Submodule Registers Figure 4-4. Time-Base Control Register TBCTLTable 4-4. Time-Base Control Register TBCTL Field Descriptions Submit Documentation FeedbackTime-Base Submodule Registers Submit Documentation FeedbackTable 4-5. Time-Base Status Register TBSTS Field Descriptions 4.2 Counter-Compare Submodule RegistersFigure 4-5. Time-Base Status Register TBSTS Figure 4-6. Counter-Compare A Register CMPATable 4-7. Counter-Compare B Register CMPB Field Descriptions Table 4-6. Counter-Compare A Register CMPA Field DescriptionsFigure 4-7. Counter-Compare B Register CMPB Counter-Compare Submodule RegistersTable 4-8. Counter-Compare Control Register CMPCTL Field Descriptions 4.3 Action-Qualifier Submodule RegistersFigure 4-8. Counter-Compare Control Register CMPCTL Action-Qualifier Submodule RegistersSubmit Documentation Feedback Figure 4-9. Action-Qualifier Output A Control Register AQCTLAAction-Qualifier Submodule Registers Submit Documentation Feedback Figure 4-10. Action-Qualifier Output B Control Register AQCTLBAction-Qualifier Submodule Registers Figure 4-11. Action-Qualifier Software Force Register AQSFRC Dead-Band Submodule Registers 4.4 Dead-Band Submodule RegistersFigure 4-13. Dead-Band Generator Control Register DBCTL Submit Documentation FeedbackDead-Band Submodule Registers Submit Documentation Feedback4.5 PWM-Chopper Submodule Control Register Figure 4-14. Dead-Band Generator Rising Edge Delay Register DBREDFigure 4-15. Dead-Band Generator Falling Edge Delay Register DBFED Figure 4-16. PWM-Chopper Control Register PCCTLTrip-Zone Submodule Control and Status Registers 4.6 Trip-Zone Submodule Control and Status RegistersPWM-Chopper Control Register PCCTL Bit Descriptions continued Submit Documentation FeedbackSubmit Documentation Feedback Figure 4-17. Trip-Zone Select Register TZSELTrip-Zone Submodule Control and Status Registers Table 4-18. Trip-Zone Control Register TZCTL Field Descriptions Figure 4-19. Trip-Zone Enable Interrupt Register TZEINTFigure 4-18. Trip-Zone Control Register TZCTL Trip-Zone Submodule Control and Status RegistersTrip-Zone Submodule Control and Status Registers Figure 4-20. Trip-Zone Flag Register TZFLGTable 4-20. Trip-Zone Flag Register TZFLG Field Descriptions Submit Documentation FeedbackTable 4-21. Trip-Zone Clear Register TZCLR Field Descriptions 4.7 Event-Trigger Submodule RegistersFigure 4-21. Trip-Zone Clear Register TZCLR Figure 4-22. Trip-Zone Force Register TZFRCBits Figure 4-23. Event-Trigger Selection Register ETSELTable 4-23. Event-Trigger Selection Register ETSEL Field Descriptions NameEvent-Trigger Submodule Registers Figure 4-24. Event-Trigger Prescale Register ETPSTable 4-24. Event-Trigger Prescale Register ETPS Field Descriptions Submit Documentation FeedbackDescription Figure 4-25. Event-Trigger Flag Register ETFLGName Submit Documentation FeedbackTable 4-26. Event-Trigger Clear Register ETCLR Field Descriptions Table 4-25. Event-Trigger Flag Register ETFLG Field DescriptionsFigure 4-26. Event-Trigger Clear Register ETCLR Event-Trigger Submodule RegistersFigure 4-27. Event-Trigger Force Register ETFRC 4.8 Proper Interrupt Initialization ProcedureProper Interrupt Initialization Procedure Table 4-27. Event-Trigger Force Register ETFRC Field DescriptionsSPRU791D-November 2004-Revised October Submit Documentation FeedbackTable A-1. Changes for Revision D Revision HistoryAppendix A SPRU791D-November 2004-Revised OctoberSection Table A-1. Changes for Revision D continuedAppendix A Submit Documentation FeedbackProducts power.ti.comIMPORTANT NOTICE Applications