Action-Qualifier Submodule Registers | Texas Instruments 28xxx

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Action-Qualifier Submodule Registers

Figure 4-8. Counter-Compare Control Register (CMPCTL)

15					10	9	8
		Reserved				SHDWBFULL	SHDWAFULL
			R-0			R-0	R-0
7	6	5	4	3	2	1	0
Reserved	SHDWBMODE	Reserved	SHDWAMODE	LOADBMODE		LOADAMODE
R-0	R/W-0	R-0	R/W-0	R/W-0		R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 4-8. Counter-Compare Control Register (CMPCTL) Field Descriptions

Bits	Name	Value	Description
15-10	Reserved		Reserved
9	SHDWBFULL		Counter-compare B (CMPB) Shadow Register Full Status Flag
			This bit self clears once a load-strobe occurs.
		0	CMPB shadow FIFO not full yet
		1	Indicates the CMPB shadow FIFO is full; a CPU write will overwrite current shadow value.
8	SHDWAFULL		Counter-compare A (CMPA) Shadow Register Full Status Flag
			The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA
			register is made. A 16-bit write to CMPAHR register will not affect the flag.
			This bit self clears once a load-strobe occurs.
		0	CMPA shadow FIFO not full yet
		1	Indicates the CMPA shadow FIFO is full, a CPU write will overwrite the current shadow
			value.
7	Reserved		Reserved
6	SHDWBMODE		Counter-compare B (CMPB) Register Operating Mode
		0	Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow
			register.
		1	Immediate mode. Only the active compare B register is used. All writes and reads directly
			access the active register for immediate compare action.
5	Reserved		Reserved
4	SHDWAMODE		Counter-compare A (CMPA) Register Operating Mode
		0	Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow
			register.
		1	Immediate mode. Only the active compare register is used. All writes and reads directly
			access the active register for immediate compare action
3-2	LOADBMODE		Active Counter-Compare B (CMPB) Load From Shadow Select Mode
			This bit has no effect in immediate mode (CMPCTL[SHDWBMODE] = 1).
		00	Load on CTR = Zero: Time-base counter equal to zero (TBCTR = 0x0000)
		01	Load on CTR = PRD: Time-base counter equal to period (TBCTR = TBPRD)
		10	Load on either CTR = Zero or CTR = PRD
		11	Freeze (no loads possible)
1-0	LOADAMODE		Active Counter-Compare A (CMPA) Load From Shadow Select Mode.
			This bit has no effect in immediate mode (CMPCTL[SHDWAMODE] = 1).
		00	Load on CTR = Zero: Time-base counter equal to zero (TBCTR = 0x0000)
		01	Load on CTR = PRD: Time-base counter equal to period (TBCTR = TBPRD)
		10	Load on either CTR = Zero or CTR = PRD
		11	Freeze (no loads possible)

4.3Action-Qualifier Submodule Registers

Figure 4-9through Figure 4-12and Table 4-9through Table 4-12provide the action-qualifier submodule register definitions.

SPRU791D–November 2004–Revised October 2007

Registers

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Texas Instruments 28xxx Action-Qualifier Submodule Registers, Counter-Compare Control Register Cmpctl Field Descriptions

Contents

Reference Guide Submit Documentation Feedback Contents Controlling a 3-Phase Interleaved DC/DC Converter List of Figures Event-Trigger Socb Pulse Generator Simplified ePWM Module List of Tables Submit Documentation Feedback Peripheral Guides Related Documentation From Texas InstrumentsData Manuals CPU Users Guides Application Reports Tools Guides TMS320C28x, C28x are trademarks of Texas Instruments Trademarks Submit Documentation Feedback Introduction Submodule Overview Introduction Multiple ePWM Modules ∙ Peripheral Bus ∙ PWM output signals EPWMxA and EPWMxB∙ Trip-zone signals TZ1 to TZ6 ∙ ADC start-of-conversion signals EPWMxSOCA and EPWMxSOCB Register Mapping EPWM Submodules and Critical Internal Signal Interconnects Counter-Compare Submodule Registers Offset Size NameDescription Time-Base Submodule Registers EPWM Submodules Submodule Configuration Parameters Submodule Configuration Parameter or OptionOverview Tbup Example 2-1. Constant Definitions Used in the Code Examples Chpenable Purpose of the Time-Base Submodule Time-Base TB Submodule Controlling and Monitoring the Time-base Submodule Time-Base Submodule RegistersRegister ∙ Down-Count Mode Key Time-Base Signals∙ Up-Down-Count Mode ∙ Up-Count Mode ∙ Active Register ∙ Time-Base Period Shadow Mode∙ Time-Base Period Immediate Load Mode Time-Base Period Shadow Register Time-Base Counter Synchronization Scheme Time-Base Counter Synchronization EPWM11SYNCO EPWM11SYNCI ∙ Software Forced Synchronization Pulse ∙ EPWMxSYNCI Synchronization Input Pulse Time-base Counter Modes and Timing Waveforms Phase Locking the Time-Base Clocks of Multiple ePWM Modules Time-Base Down-Count Mode Waveforms 11. Counter-Compare Submodule Counter-Compare CC Submodule Register Name Address Offset Purpose of the Counter-Compare SubmoduleControlling and Monitoring the Counter-Compare Submodule Counter-Compare Submodule Registers ∙ Immediate Load Mode Count Mode Timing WaveformsCounter-Compare Submodule Key Signals ∙ Shadow Mode CTR=CMPB CTR=CMPA CTR = Cmpb Action-Qualifier AQ Submodule Purpose of the Action-Qualifier SubmoduleAction-Qualifier Submodule Registers ∙ Toggle Action-Qualifier Submodule Possible Input Events∙ Set High ∙ Clear Low TB Counter equals Actions Action-Qualifier Event Priority Action-Qualifier Event Priority for Up-Down-Count ModeAction-Qualifier Event Priority for Up-Count Mode 10. Action-Qualifier Event Priority for Down-Count Mode When using up-count mode to generate an asymmetric PWM Waveforms for Common ConfigurationsUse up-down-count mode to generate a symmetric PWM Use up-down-count mode to generate an asymmetric PWM 20. Up-Down-Count Mode Symmetrical Waveform Tbctr Example 2-2. Code Sample for Figure Value EPWMxA EPWMxB Tbclk = Sysclkout Example 2-3. Code Sample for Figure EdgePosA Example 2-4. Code Sample for Figure Example 2-5. Code Sample for Figure Tbctr Example 2-6. Code Sample for Figure EPWMxA EPWMxB Example 2-7. Code Sample for Figure 12. Dead-Band Generator Submodule Registers Dead-Band Generator DB SubmodulePurpose of the Dead-Band Submodule Controlling and Monitoring the Dead-Band Submodule ∙ Polarity Control ∙ Output Mode ControlOperational Highlights for the Dead-Band Submodule ∙ Input Source Selection 13. Classical Dead-Band Operating Modes Mode Description 29. Dead-Band Waveforms for Typical Cases 0% Duty 100% FED = Dbfed × Ttbclk RED = Dbred × Ttbclk Dead-Band Delay in μS Operational Highlights for the PWM-Chopper Submodule PWM-Chopper PC SubmodulePurpose of the PWM-Chopper Submodule Controlling the PWM-Chopper Submodule 31. PWM-Chopper Submodule Operational Details Waveforms One-Shot Pulse 16. Possible Pulse Width Values for Sysclkout = 100 MHzOSHTWTHz Period Duty Cycle Control Purpose of the Trip-Zone Submodule Trip-Zone TZ Submodule ∙ Cycle-by-Cycle CBC Controlling and Monitoring the Trip-Zone SubmoduleOperational Highlights for the Trip-Zone Submodule 17. Trip-Zone Submodule Registers Scenario B Example 2-8. Trip-Zone Configurations18. Possible Actions On a Trip Event Scenario a Generating Trip Event Interrupts 36. Trip-Zone Submodule Mode Control Logic 37. Trip-Zone Submodule Interrupt Logic Event-Trigger ET Submodule Operational Overview of the Event-Trigger Submodule CTR=CMPB CTRD=CMPB 19. Event-Trigger Submodule Registers 41. Event-Trigger Interrupt Generator 42. Event-Trigger Soca Pulse Generator Submit Documentation Feedback Controlling Multiple Buck Converters With Independent Applications to Power Topologies Overview of Multiple Modules Key Configuration Capabilities CTR=0 EPWM1B CTR=CMPB Control of Four Buck Stages. Here FPWM1≠ FPWM2≠ FPWM3≠ FPWM4 Buck Waveforms for -3Note Only three bucks shown here 500 Example 3-1. Configuration for Example in Figure Control of Four Buck Stages. Note FPWM2 = N x FPWM1 Controlling Multiple Buck Converters With Same Frequencies Buck Waveforms for -5Note FPWM2 = FPWM1 Example 3-2. Code Snippet for Configuration in Figure Control of Two Half-H Bridge Stages FPWM2 = N x FPWM1 Controlling Multiple Half H-Bridge HHB Converters Half-H Bridge Waveforms for -7Note Here FPWM2 = FPWM1 Example 3-3. Code Snippet for Configuration in Figure Controlling Dual 3-Phase Inverters for Motors ACI and Pmsm EPWM1A 10 -Phase Inverter Waveforms for -9Only One Inverter Shown Example 3-4. Code Snippet for Configuration in Figure 11. Configuring Two PWM Modules for Phase Control Controlling a 3-Phase Interleaved DC/DC Converter Controlling a 3-Phase Interleaved DC/DC Converter 13. Control of a 3-Phase Interleaved DC/DC Converter 14 -Phase Interleaved DC/DC Converter Waveforms for Figure Example 3-5. Code Snippet for Configuration in Figure 15. Controlling a Full-H Bridge Stage FPWM2 = FPWM1 16. ZVS Full-H Bridge Waveforms Example 3-6. Code Snippet for Configuration in Figure Submit Documentation Feedback Proper Interrupt Initialization Procedure PWM-Chopper Submodule Control RegisterTrip-Zone Submodule Control and Status Registers Time-Base Counter Register Tbctr Field Descriptions Time-Base Phase Register Tbphs Field DescriptionsTime-Base Submodule Registers Time-Base Period Register Tbprd Field Descriptions Bit Field Value Description Time-Base Control Register Tbctl Field Descriptions Software Forced Synchronization Pulse Counter-Compare Submodule Registers Time-Base Status Register Tbsts Field DescriptionsBit Field Counter-Compare a Register Cmpa Field Descriptions Counter-Compare B Register Cmpb Field DescriptionsBits Name Description Counter-Compare Control Register Cmpctl Field Descriptions Action-Qualifier Submodule Registers CBD CBU CAD CAU PRD ZRO Bits NameCBD 10. Action-Qualifier Output B Control Register Aqctlb Rldcsf Otsfb Actsfb Otsfa Actsfa RldcsfCsfb Csfa Dead-Band Submodule Registers CsfbInmode Polsel Outmode Inmode Reserved PWM-Chopper Submodule Control Register16. PWM-Chopper Control Register Pcctl Bit Descriptions Name Value Description Trip-Zone Submodule Control and Status Registers PWM-Chopper Control Register Pcctl Bit DescriptionsChpduty CBC6 OSHT6 OSHT5 OSHT4 OSHT3 OSHT2 OSHT1CBC6 CBC5 CBC4 CBC3 CBC2 CBC1 OSHT6 OST CBC 18. Trip-Zone Control Register Tzctl Field DescriptionsTZB TZA TZB OST CBC INT 20. Trip-Zone Flag Register Tzflg Field Descriptions Event-Trigger Submodule Registers 21. Trip-Zone Clear Register Tzclr Field Descriptions22. Trip-Zone Force Register Tzfrc Field Descriptions 23. Event-Trigger Selection Register Etsel Name Description 24. Event-Trigger Prescale Register Etps Field Descriptions Socb Soca 24. Event-Trigger Prescale Register Etps Field Descriptions 25. Event-Trigger Flag Register Etflg Field Descriptions 26. Event-Trigger Clear Register Etclr Field DescriptionsSocb 27. Event-Trigger Force Register Etfrc Field Descriptions Proper Interrupt Initialization Procedure 116 Location Modifications, Additions, and Deletions Table A-1. Changes for Revision D Appendix a Important Notice