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Texas Instruments TMS320x28xx, 28xxx Time-Base Submodule Registers, Submit Documentation Feedback

Models: 28xxx TMS320x28xx

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Time-Base Submodule Registers

Table 4-4. Time-Base Control Register (TBCTL) Field Descriptions (continued)

Bit	Field	Value	Description
6	SWFSYNC		Software Forced Synchronization Pulse
		0	Writing a 0 has no effect and reads always return a 0.
		1	Writing a 1 forces a one-time synchronization pulse to be generated.
			This event is ORed with the EPWMxSYNCI input of the ePWM module.
			SWFSYNC is valid (operates) only when EPWMxSYNCI is selected by SYNCOSEL = 00.
5:4	SYNCOSEL		Synchronization Output Select. These bits select the source of the EPWMxSYNCO signal.
		00	EPWMxSYNC:
		01	CTR = zero: Time-base counter equal to zero (TBCTR = 0x0000)
		10	CTR = CMPB : Time-base counter equal to counter-compare B (TBCTR = CMPB)
		11	Disable EPWMxSYNCO signal
3	PRDLD		Active Period Register Load From Shadow Register Select
		0	The period register (TBPRD) is loaded from its shadow register when the time-base counter,
			TBCTR, is equal to zero.
			A write or read to the TBPRD register accesses the shadow register.
		1	Load the TBPRD register immediately without using a shadow register.
			A write or read to the TBPRD register directly accesses the active register.
2	PHSEN		Counter Register Load From Phase Register Enable
		0	Do not load the time-base counter (TBCTR) from the time-base phase register (TBPHS)
		1	Load the time-base counter with the phase register when an EPWMxSYNCI input signal occurs or
			when a software synchronization is forced by the SWFSYNC bit.
1:0	CTRMODE		Counter Mode
			The time-base counter mode is normally configured once and not changed during normal operation.
			If you change the mode of the counter, the change will take effect at the next TBCLK edge and the
			current counter value shall increment or decrement from the value before the mode change.
			These bits set the time-base counter mode of operation as follows:
		00	Up-count mode
		01	Down-count mode
		10	Up-down-count mode
		11	Stop-freeze counter operation (default on reset)

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Registers

SPRU791D–November 2004–Revised October 2007

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Texas Instruments TMS320x28xx, 28xxx manual Time-Base Submodule Registers, Submit Documentation Feedback

Contents

Reference Guide TMS320x28xx, 28xxx Enhanced Pulse Width Modulator ePWM ModuleSPRU791D-November 2004-Revised October Submit Documentation FeedbackContents Controlling Multiple Half H-Bridge HHB Converters List of Figures List of FiguresEvent-Trigger SOCB Pulse Generator List of Tables SPRU791D-November 2004-Revised October Submit Documentation FeedbackRead This First PrefaceRelated Documentation From Texas Instruments Data ManualsTools Guides Application ReportsRelated Documentation From Texas Instruments Trademarks TMS320C28x, C28x are trademarks of Texas InstrumentsSPRU791D-November 2004-Revised October Submit Documentation FeedbackIntroduction ChapterIntroduction Submodule Overview1.1 Introduction 1.2 Submodule OverviewFigure 1-1. Multiple ePWM Modules Submodule OverviewFigure 1-2. Submodules and Signal Connections for an ePWM Module ∙ PWM output signals EPWMxA and EPWMxB∙ Trip-zone signals TZ1 to TZ6 ∙ ADC start-of-conversion signals EPWMxSOCA and EPWMxSOCB1.3 Register Mapping Register MappingRegister Mapping OffsetSubmit Documentation Feedback ePWM Submodules OverviewTime-Base TB Submodule Counter-Compare CC SubmoduleTable 2-1. Submodule Configuration Parameters 2.1 OverviewOverview Submit Documentation FeedbackTable 2-1. Submodule Configuration Parameters continued Example 2-1. Constant Definitions Used in the Code ExamplesOverview Submit Documentation FeedbackExample 2-1. Constant Definitions Used in the Code Examples continued OverviewSubmit Documentation Feedback Figure 2-1. Time-Base Submodule Block Diagram 2.2 Time-Base TB Submodule2.2.1 Purpose of the Time-Base Submodule Figure 2-2. Time-Base Submodule Signals and Registers 2.2.2 Controlling and Monitoring the Time-base SubmoduleTable 2-2. Time-Base Submodule Registers Table 2-3. Key Time-Base Signals 2.2.3 Calculating PWM Period and Frequency∙ Up-Down-Count Mode ∙ Up-Count ModeFigure 2-3. Time-Base Frequency and Period 2.2.3.1 Time-Base Period Shadow Register∙ Active Register ∙ Shadow Register2.2.3.2 Time-Base Counter Synchronization Figure 2-4. Time-Base Counter Synchronization SchemeFigure 2-5. Time-Base Counter Synchronization Scheme Figure 2-6. Time-Base Counter Synchronization Scheme ∙ EPWMxSYNCI Synchronization Input Pulse∙ Software Forced Synchronization Pulse 2.2.4 Phase Locking the Time-Base Clocks of Multiple ePWM Modules 2.2.5 Time-base Counter Modes and Timing WaveformsFigure 2-7. Time-Base Up-Count Mode Waveforms Figure 2-8. Time-Base Down-Count Mode Waveforms EventTime-Base TB Submodule 2.3 Counter-Compare CC Submodule EventFigure 2-11 illustrates the counter-compare submodule within the ePWM Figure 2-11. Counter-Compare Submodule2.3.1 Purpose of the Counter-Compare Submodule 2.3.2 Controlling and Monitoring the Counter-Compare SubmoduleTable 2-4. Counter-Compare Submodule Registers Figure 2-12. Detailed View of the Counter-Compare SubmoduleTable 2-5. Counter-Compare Submodule Key Signals 2.3.3 Operational Highlights for the Counter-Compare Submodule2.3.4 Count Mode Timing Waveforms ∙ Shadow Mode∙ Up-down-count mode used to generate a symmetrical PWM waveform Figure 2-13. Counter-Compare Event Waveforms in Up-Count ModeFigure 2-14. Counter-Compare Events in Down-Count Mode Counter-Compare CC SubmoduleSynchronization Event Synchronization Event2.4 Action-Qualifier AQ Submodule 2.4.1 Purpose of the Action-Qualifier SubmoduleFigure 2-17. Action-Qualifier Submodule Table 2-6. Action-Qualifier Submodule RegistersFigure 2-18. Action-Qualifier Submodule Inputs and Outputs Table 2-7. Action-Qualifier Submodule Possible Input Events∙ Set High ∙ Clear LowPage 2.4.3 Action-Qualifier Event Priority Table 2-8. Action-Qualifier Event Priority for Up-Down-Count ModeTable 2-9. Action-Qualifier Event Priority for Up-Count Mode Table 2-10. Action-Qualifier Event Priority for Down-Count Mode2.4.4 Waveforms for Common Configurations When using up-count mode to generate an asymmetric PWMSee the Using Enhanced Pulse Width Modulator ePWM Module for 0-100% Table 2-11. Behavior if CMPA/CMPB is Greater than the PeriodFigure 2-20. Up-Down-Count Mode Symmetrical Waveform EPWMxB-Active High Example 2-2. Code Sample for FigureAction-Qualifier AQ Submodule EPWMxB-Active Low Action-Qualifier AQ SubmoduleExample 2-3. Code Sample for Figure EPWMxAAction-Qualifier AQ Submodule Submit Documentation FeedbackExample 2-4. Code Sample for Figure Action-Qualifier AQ SubmoduleSubmit Documentation Feedback EPWMxA and EPWMxB - Active Low Example 2-5. Code Sample for FigureAction-Qualifier AQ Submodule EPWMxA and EPWMxB - Complementary Example 2-6. Code Sample for FigureAction-Qualifier AQ Submodule EPWMxA-Active Low Example 2-7. Code Sample for FigureAction-Qualifier AQ Submodule Submit Documentation Feedback2.5 Dead-Band Generator DB Submodule 2.5.1 Purpose of the Dead-Band Submodule2.5.2 Controlling and Monitoring the Dead-Band Submodule Figure 2-27. DeadBand SubmoduleFigure 2-28. Configuration Options for the Dead-Band Submodule ∙ Mode 2-5 Classical Dead-Band Polarity Settings2.5.3 Operational Highlights for the Dead-Band Submodule ∙ Input Source Selectionaction-qualifier submodule to generate the signal as shown for EPWMxA Table 2-13. Classical Dead-Band Operating ModesDead-Band Generator DB Submodule Submit Documentation FeedbackFigure 2-29 shows waveforms for typical cases where 0% duty 100% Figure 2-29. Dead-Band Waveforms for Typical Cases 0% Duty 100%Dead-Band Generator DB Submodule Submit Documentation FeedbackFED = DBFED × TTBCLK RED = DBRED × TTBCLK 2.6 PWM-Chopper PC Submodule 2.6.1 Purpose of the PWM-Chopper Submodule2.6.2 Controlling the PWM-Chopper Submodule 2.6.3 Operational Highlights for the PWM-Chopper Submodule2.6.4 Waveforms Figure 2-31. PWM-Chopper Submodule Operational DetailsPWM-Chopper PC Submodule 2.6.4.1 One-Shot Pulse PulsesTable 2-16. Possible Pulse Width Values for SYSCLKOUT = 100 MHz Start OSHT pulse EPWMxA in PSCLK Prog. pulse width OSHTWTH OSHT2.6.4.2 Duty Cycle Control Sustaining Pulses87.5% PSCLK Period2.7 Trip-Zone TZ Submodule 2.7.1 Purpose of the Trip-Zone SubmoduleFigure 2-35. Trip-Zone Submodule 2.7.2 Controlling and Monitoring the Trip-Zone Submodule 2.7.3 Operational Highlights for the Trip-Zone SubmoduleTable 2-17. Trip-Zone Submodule Registers ∙ Cycle-by-Cycle CBCExample 2-8. Trip-Zone Configurations Table 2-18. Possible Actions On a Trip EventScenario A Scenario B2.7.4 Generating Trip Event Interrupts Figure 2-36. Trip-Zone Submodule Mode Control LogicTrip-Zone TZ Submodule 2.8 Event-Trigger ET Submodule Figure 2-37. Trip-Zone Submodule Interrupt LogicFigure 2-38. Event-Trigger Submodule Signals 2.8.1 Operational Overview of the Event-Trigger SubmoduleTable 2-19. Event-Trigger Submodule Registers Figure 2-41. Event-Trigger Interrupt Generator input =Figure 2-42. Event-Trigger SOCA Pulse Generator Figure 2-43. Event-Trigger SOCB Pulse GeneratorEvent-Trigger ET Submodule Submit Documentation FeedbackSPRU791D-November 2004-Revised October Submit Documentation FeedbackApplications to Power Topologies Key Configuration CapabilitiesOverview of Multiple Modules Frequencies3.2 Key Configuration Capabilities 3.1 Overview of Multiple ModulesFigure 3-1. Simplified ePWM Module 3.3 Controlling Multiple Buck Converters With Independent Frequencies Controlling Multiple Buck Converters With Independent FrequenciesControlling Multiple Buck Converters With Independent Frequencies Submit Documentation FeedbackControlling Multiple Buck Converters With Independent Frequencies Indicates this event triggers an ADC startExample 3-1. Configuration for Example in Figure Controlling Multiple Buck Converters With Independent FrequenciesSubmit Documentation Feedback 3.4 Controlling Multiple Buck Converters With Same Frequencies Figure 3-5. Control of Four Buck Stages. Note FPWM2 = N x FPWM1Figure 3-6. Buck Waveforms for Figure 3-5 Note FPWM2 = FPWM1 Controlling Multiple Buck Converters With Same FrequenciesExample 3-2. Code Snippet for Configuration in Figure Controlling Multiple Buck Converters With Same FrequenciesSubmit Documentation Feedback 3.5 Controlling Multiple Half H-Bridge HHB Converters Figure 3-7. Control of Two Half-H Bridge Stages FPWM2 = N x FPWM1Controlling Multiple Half H-Bridge HHB Converters 3.6 Controlling Dual 3-Phase Inverters for Motors ACI and PMSM Example 3-3. Code Snippet for Configuration in FigureControlling Dual 3-Phase Inverters for Motors ACI and PMSM Submit Documentation FeedbackControlling Dual 3-Phase Inverters for Motors ACI and PMSM Example 3-4. Code Snippet for Configuration in Figure Controlling Dual 3-Phase Inverters for Motors ACI and PMSMSubmit Documentation Feedback 3.7 Practical Applications Using Phase Control Between PWM Modules Figure 3-11. Configuring Two PWM Modules for Phase Control3.8 Controlling a 3-Phase Interleaved DC/DC Converter Figure 3-13. Control of a 3-Phase Interleaved DC/DC Converter Controlling a 3-Phase Interleaved DC/DC Converter=240 Figure 3-14. 3-Phase Interleaved DC/DC Converter Waveforms for Figure Controlling a 3-Phase Interleaved DC/DC ConverterExample 3-5. Code Snippet for Configuration in Figure Controlling a 3-Phase Interleaved DC/DC ConverterSubmit Documentation Feedback 3.9 Controlling Zero Voltage Switched Full Bridge ZVSFB Converter Figure 3-15. Controlling a Full-H Bridge Stage FPWM2 = FPWM1Controlling Zero Voltage Switched Full Bridge ZVSFB Converter Figure 3-16. ZVS Full-H Bridge WaveformsExample 3-6. Code Snippet for Configuration in Figure Controlling Zero Voltage Switched Full Bridge ZVSFB ConverterSubmit Documentation Feedback SPRU791D-November 2004-Revised October Submit Documentation FeedbackRegisters Time-Base Submodule RegistersCounter-Compare Submodule Registers Action-Qualifier Submodule RegistersFigure 4-2. Time-Base Phase Register TBPHS Table 4-2. Time-Base Phase Register TBPHS Field Descriptions4.1 Time-Base Submodule Registers Figure 4-1. Time-Base Period Register TBPRDFigure 4-4. Time-Base Control Register TBCTL Table 4-4. Time-Base Control Register TBCTL Field DescriptionsTime-Base Submodule Registers Submit Documentation FeedbackTime-Base Submodule Registers Submit Documentation Feedback4.2 Counter-Compare Submodule Registers Figure 4-5. Time-Base Status Register TBSTSTable 4-5. Time-Base Status Register TBSTS Field Descriptions Figure 4-6. Counter-Compare A Register CMPATable 4-6. Counter-Compare A Register CMPA Field Descriptions Figure 4-7. Counter-Compare B Register CMPBTable 4-7. Counter-Compare B Register CMPB Field Descriptions Counter-Compare Submodule Registers4.3 Action-Qualifier Submodule Registers Figure 4-8. Counter-Compare Control Register CMPCTLTable 4-8. Counter-Compare Control Register CMPCTL Field Descriptions Action-Qualifier Submodule RegistersFigure 4-9. Action-Qualifier Output A Control Register AQCTLA Action-Qualifier Submodule RegistersSubmit Documentation Feedback Figure 4-10. Action-Qualifier Output B Control Register AQCTLB Action-Qualifier Submodule RegistersSubmit Documentation Feedback Figure 4-11. Action-Qualifier Software Force Register AQSFRC 4.4 Dead-Band Submodule Registers Figure 4-13. Dead-Band Generator Control Register DBCTLDead-Band Submodule Registers Submit Documentation FeedbackDead-Band Submodule Registers Submit Documentation FeedbackFigure 4-14. Dead-Band Generator Rising Edge Delay Register DBRED Figure 4-15. Dead-Band Generator Falling Edge Delay Register DBFED4.5 PWM-Chopper Submodule Control Register Figure 4-16. PWM-Chopper Control Register PCCTL4.6 Trip-Zone Submodule Control and Status Registers PWM-Chopper Control Register PCCTL Bit Descriptions continuedTrip-Zone Submodule Control and Status Registers Submit Documentation FeedbackFigure 4-17. Trip-Zone Select Register TZSEL Trip-Zone Submodule Control and Status RegistersSubmit Documentation Feedback Figure 4-19. Trip-Zone Enable Interrupt Register TZEINT Figure 4-18. Trip-Zone Control Register TZCTLTable 4-18. Trip-Zone Control Register TZCTL Field Descriptions Trip-Zone Submodule Control and Status RegistersFigure 4-20. Trip-Zone Flag Register TZFLG Table 4-20. Trip-Zone Flag Register TZFLG Field DescriptionsTrip-Zone Submodule Control and Status Registers Submit Documentation Feedback4.7 Event-Trigger Submodule Registers Figure 4-21. Trip-Zone Clear Register TZCLRTable 4-21. Trip-Zone Clear Register TZCLR Field Descriptions Figure 4-22. Trip-Zone Force Register TZFRCFigure 4-23. Event-Trigger Selection Register ETSEL Table 4-23. Event-Trigger Selection Register ETSEL Field DescriptionsBits NameFigure 4-24. Event-Trigger Prescale Register ETPS Table 4-24. Event-Trigger Prescale Register ETPS Field DescriptionsEvent-Trigger Submodule Registers Submit Documentation FeedbackFigure 4-25. Event-Trigger Flag Register ETFLG NameDescription Submit Documentation FeedbackTable 4-25. Event-Trigger Flag Register ETFLG Field Descriptions Figure 4-26. Event-Trigger Clear Register ETCLRTable 4-26. Event-Trigger Clear Register ETCLR Field Descriptions Event-Trigger Submodule Registers4.8 Proper Interrupt Initialization Procedure Proper Interrupt Initialization ProcedureFigure 4-27. Event-Trigger Force Register ETFRC Table 4-27. Event-Trigger Force Register ETFRC Field DescriptionsSPRU791D-November 2004-Revised October Submit Documentation FeedbackRevision History Appendix ATable A-1. Changes for Revision D SPRU791D-November 2004-Revised OctoberTable A-1. Changes for Revision D continued Appendix ASection Submit Documentation Feedbackpower.ti.com IMPORTANT NOTICEProducts Applications