Texas Instruments 28xxx, TMS320x28xx instruction

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Action-Qualifier Submodule Registers

Figure 4-10. Action-Qualifier Output B Control Register (AQCTLB)

15			12	11	10	9	8
	Reserved				CBD		CBU
	R-0				R/W-0		R/W-0
7	6	5	4	3	2	1	0
	CAD		CAU		PRD		ZRO
	R/W-0		R/W-0		R/W-0		R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 4-10. Action-Qualifier Output B Control Register (AQCTLB) Field Descriptions

Bits	Name	Value	Description
15-12	Reserved
11-10	CBD		Action when the counter equals the active CMPB register and the counter is decrementing.
		00	Do nothing (action disabled)
		01	Clear: force EPWMxB output low.
		10	Set: force EPWMxB output high.
		11	Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low.
9-8	CBU		Action when the counter equals the active CMPB register and the counter is incrementing.
		00	Do nothing (action disabled)
		01	Clear: force EPWMxB output low.
		10	Set: force EPWMxB output high.
		11	Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low.
7-6	CAD		Action when the counter equals the active CMPA register and the counter is decrementing.
		00	Do nothing (action disabled)
		01	Clear: force EPWMxB output low.
		10	Set: force EPWMxB output high.
		11	Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low.
5-4	CAU		Action when the counter equals the active CMPA register and the counter is incrementing.
		00	Do nothing (action disabled)
		01	Clear: force EPWMxB output low.
		10	Set: force EPWMxB output high.
		11	Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low.
3-2	PRD		Action when the counter equals the period.
			Note: By definition, in count up-down mode when the counter equals period the direction is defined
			as 0 or counting down.
		00	Do nothing (action disabled)
		01	Clear: force EPWMxB output low.
		10	Set: force EPWMxB output high.
		11	Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low.
1-0	ZRO		Action when counter equals zero.
			Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1
			or counting up.
		00	Do nothing (action disabled)
		01	Clear: force EPWMxB output low.
		10	Set: force EPWMxB output high.
		11	Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low.

SPRU791D–November 2004–Revised October 2007	Registers	101
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Image 101

Texas Instruments 28xxx, TMS320x28xx manual Action-Qualifier Output B Control Register Aqctlb

Contents

Reference Guide Submit Documentation Feedback Contents Controlling a 3-Phase Interleaved DC/DC Converter List of Figures Event-Trigger Socb Pulse Generator Simplified ePWM Module List of Tables Submit Documentation Feedback Data Manuals Related Documentation From Texas InstrumentsCPU Users Guides Peripheral Guides Application Reports Tools Guides TMS320C28x, C28x are trademarks of Texas Instruments Trademarks Submit Documentation Feedback Introduction Submodule Overview Introduction Multiple ePWM Modules ∙ Trip-zone signals TZ1 to TZ6 ∙ PWM output signals EPWMxA and EPWMxB∙ ADC start-of-conversion signals EPWMxSOCA and EPWMxSOCB ∙ Peripheral Bus Register Mapping EPWM Submodules and Critical Internal Signal Interconnects Description Offset Size NameTime-Base Submodule Registers Counter-Compare Submodule Registers EPWM Submodules Overview Submodule Configuration ParametersSubmodule Configuration Parameter or Option Tbup Example 2-1. Constant Definitions Used in the Code Examples Chpenable Purpose of the Time-Base Submodule Time-Base TB Submodule Register Controlling and Monitoring the Time-base SubmoduleTime-Base Submodule Registers ∙ Up-Down-Count Mode Key Time-Base Signals∙ Up-Count Mode ∙ Down-Count Mode ∙ Time-Base Period Immediate Load Mode ∙ Time-Base Period Shadow ModeTime-Base Period Shadow Register ∙ Active Register Time-Base Counter Synchronization Scheme Time-Base Counter Synchronization EPWM11SYNCO EPWM11SYNCI ∙ Software Forced Synchronization Pulse ∙ EPWMxSYNCI Synchronization Input Pulse Time-base Counter Modes and Timing Waveforms Phase Locking the Time-Base Clocks of Multiple ePWM Modules Time-Base Down-Count Mode Waveforms 11. Counter-Compare Submodule Counter-Compare CC Submodule Controlling and Monitoring the Counter-Compare Submodule Purpose of the Counter-Compare SubmoduleCounter-Compare Submodule Registers Register Name Address Offset Counter-Compare Submodule Key Signals Count Mode Timing Waveforms∙ Shadow Mode ∙ Immediate Load Mode CTR=CMPB CTR=CMPA CTR = Cmpb Action-Qualifier Submodule Registers Action-Qualifier AQ SubmodulePurpose of the Action-Qualifier Submodule ∙ Set High Action-Qualifier Submodule Possible Input Events∙ Clear Low ∙ Toggle TB Counter equals Actions Action-Qualifier Event Priority for Up-Count Mode Action-Qualifier Event Priority for Up-Down-Count Mode10. Action-Qualifier Event Priority for Down-Count Mode Action-Qualifier Event Priority Use up-down-count mode to generate a symmetric PWM Waveforms for Common ConfigurationsUse up-down-count mode to generate an asymmetric PWM When using up-count mode to generate an asymmetric PWM 20. Up-Down-Count Mode Symmetrical Waveform Tbctr Example 2-2. Code Sample for Figure Value EPWMxA EPWMxB Tbclk = Sysclkout Example 2-3. Code Sample for Figure EdgePosA Example 2-4. Code Sample for Figure Example 2-5. Code Sample for Figure Tbctr Example 2-6. Code Sample for Figure EPWMxA EPWMxB Example 2-7. Code Sample for Figure Purpose of the Dead-Band Submodule Dead-Band Generator DB SubmoduleControlling and Monitoring the Dead-Band Submodule 12. Dead-Band Generator Submodule Registers Operational Highlights for the Dead-Band Submodule ∙ Output Mode Control∙ Input Source Selection ∙ Polarity Control 13. Classical Dead-Band Operating Modes Mode Description 29. Dead-Band Waveforms for Typical Cases 0% Duty 100% FED = Dbfed × Ttbclk RED = Dbred × Ttbclk Dead-Band Delay in μS Purpose of the PWM-Chopper Submodule PWM-Chopper PC SubmoduleControlling the PWM-Chopper Submodule Operational Highlights for the PWM-Chopper Submodule 31. PWM-Chopper Submodule Operational Details Waveforms OSHTWTHz One-Shot Pulse16. Possible Pulse Width Values for Sysclkout = 100 MHz Period Duty Cycle Control Purpose of the Trip-Zone Submodule Trip-Zone TZ Submodule Operational Highlights for the Trip-Zone Submodule Controlling and Monitoring the Trip-Zone Submodule17. Trip-Zone Submodule Registers ∙ Cycle-by-Cycle CBC 18. Possible Actions On a Trip Event Example 2-8. Trip-Zone ConfigurationsScenario a Scenario B Generating Trip Event Interrupts 36. Trip-Zone Submodule Mode Control Logic 37. Trip-Zone Submodule Interrupt Logic Event-Trigger ET Submodule Operational Overview of the Event-Trigger Submodule CTR=CMPB CTRD=CMPB 19. Event-Trigger Submodule Registers 41. Event-Trigger Interrupt Generator 42. Event-Trigger Soca Pulse Generator Submit Documentation Feedback Controlling Multiple Buck Converters With Independent Applications to Power Topologies Overview of Multiple Modules Key Configuration Capabilities CTR=0 EPWM1B CTR=CMPB Control of Four Buck Stages. Here FPWM1≠ FPWM2≠ FPWM3≠ FPWM4 Buck Waveforms for -3Note Only three bucks shown here 500 Example 3-1. Configuration for Example in Figure Control of Four Buck Stages. Note FPWM2 = N x FPWM1 Controlling Multiple Buck Converters With Same Frequencies Buck Waveforms for -5Note FPWM2 = FPWM1 Example 3-2. Code Snippet for Configuration in Figure Control of Two Half-H Bridge Stages FPWM2 = N x FPWM1 Controlling Multiple Half H-Bridge HHB Converters Half-H Bridge Waveforms for -7Note Here FPWM2 = FPWM1 Example 3-3. Code Snippet for Configuration in Figure Controlling Dual 3-Phase Inverters for Motors ACI and Pmsm EPWM1A 10 -Phase Inverter Waveforms for -9Only One Inverter Shown Example 3-4. Code Snippet for Configuration in Figure 11. Configuring Two PWM Modules for Phase Control Controlling a 3-Phase Interleaved DC/DC Converter Controlling a 3-Phase Interleaved DC/DC Converter 13. Control of a 3-Phase Interleaved DC/DC Converter 14 -Phase Interleaved DC/DC Converter Waveforms for Figure Example 3-5. Code Snippet for Configuration in Figure 15. Controlling a Full-H Bridge Stage FPWM2 = FPWM1 16. ZVS Full-H Bridge Waveforms Example 3-6. Code Snippet for Configuration in Figure Submit Documentation Feedback Trip-Zone Submodule Control and Status Registers Proper Interrupt Initialization ProcedurePWM-Chopper Submodule Control Register Time-Base Submodule Registers Time-Base Phase Register Tbphs Field DescriptionsTime-Base Period Register Tbprd Field Descriptions Time-Base Counter Register Tbctr Field Descriptions Bit Field Value Description Time-Base Control Register Tbctl Field Descriptions Software Forced Synchronization Pulse Bit Field Counter-Compare Submodule RegistersTime-Base Status Register Tbsts Field Descriptions Bits Name Description Counter-Compare a Register Cmpa Field DescriptionsCounter-Compare B Register Cmpb Field Descriptions Counter-Compare Control Register Cmpctl Field Descriptions Action-Qualifier Submodule Registers CBD CBD CBU CAD CAU PRD ZROBits Name 10. Action-Qualifier Output B Control Register Aqctlb Csfb Csfa Rldcsf Otsfb Actsfb Otsfa ActsfaRldcsf Inmode Polsel Outmode Dead-Band Submodule RegistersCsfb Inmode 16. PWM-Chopper Control Register Pcctl Bit Descriptions PWM-Chopper Submodule Control RegisterName Value Description Reserved Chpduty Trip-Zone Submodule Control and Status RegistersPWM-Chopper Control Register Pcctl Bit Descriptions CBC6 CBC5 CBC4 CBC3 CBC2 CBC1 OSHT6 OSHT5 OSHT4 OSHT3 OSHT2 OSHT1OSHT6 CBC6 TZB TZA 18. Trip-Zone Control Register Tzctl Field DescriptionsTZB OST CBC OST CBC INT 20. Trip-Zone Flag Register Tzflg Field Descriptions 22. Trip-Zone Force Register Tzfrc Field Descriptions Event-Trigger Submodule Registers21. Trip-Zone Clear Register Tzclr Field Descriptions 23. Event-Trigger Selection Register Etsel Name Description 24. Event-Trigger Prescale Register Etps Field Descriptions Socb Soca 24. Event-Trigger Prescale Register Etps Field Descriptions Socb 25. Event-Trigger Flag Register Etflg Field Descriptions26. Event-Trigger Clear Register Etclr Field Descriptions 27. Event-Trigger Force Register Etfrc Field Descriptions Proper Interrupt Initialization Procedure 116 Location Modifications, Additions, and Deletions Table A-1. Changes for Revision D Appendix a Important Notice