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Texas Instruments 28xxx manual 4. Time-Base Control Register TBCTL, Time-Base Submodule Registers

Models: 28xxx TMS320x28xx

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Figure 4-4. Time-Base Control Register (TBCTL)

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Time-Base Submodule Registers

Figure 4-4. Time-Base Control Register (TBCTL)

15	14	13	12		10	9	8
FREE, SOFT		PHSDIR		CLKDIV			HSPCLKDIV
R/W-0		R/W-0		R/W-0			R/W-0,0,1
7	6	5	4	3	2	1	0
HSPCLKDIV	SWFSYNC	SYNCOSEL		PRDLD	PHSEN		CTRMODE
R/W-0,0,1	R/W-0	R/W-0		R/W-0	R/W-0		R/W-11
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 4-4. Time-Base Control Register (TBCTL) Field Descriptions

Bit	Field	Value	Description
15:14	FREE, SOFT		Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during
			emulation events:
		00	Stop after the next time-base counter increment or decrement
		01	Stop when counter completes a whole cycle:
			∙	Up-count mode: stop when the time-base counter = period (TBCTR = TBPRD)
			∙	Down-count mode: stop when the time-base counter = 0x0000 (TBCTR = 0x0000)
			∙	Up-down-count mode: stop when the time-base counter = 0x0000 (TBCTR = 0x0000)
		1X	Free run
13	PHSDIR		Phase Direction Bit.
			This bit is only used when the time-base counter is configured in the up-down-count mode. The
			PHSDIR bit indicates the direction the time-base counter (TBCTR) will count after a synchronization
			event occurs and a new phase value is loaded from the phase (TBPHS) register. This is
			irrespective of the direction of the counter before the synchronization event..
			In the up-count and down-count modes this bit is ignored.
		0	Count down after the synchronization event.
		1	Count up after the synchronization event.
12:10	CLKDIV		Time-base Clock Prescale Bits
			These bits determine part of the time-base clock prescale value.
			TBCLK = SYSCLKOUT / (HSPCLKDIV × CLKDIV)
		000	/1 (default on reset)
		001	/2
		010	/4
		011	/8
		100	/16
		101	/32
		110	/64
		111	/128
9:7	HSPCLKDIV		High Speed Time-base Clock Prescale Bits
			These bits determine part of the time-base clock prescale value.
			TBCLK = SYSCLKOUT / (HSPCLKDIV × CLKDIV)
			This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager
			(EV) peripheral.
		000	/1
		001	/2 (default on reset)
		010	/4
		011	/6
		100	/8
		101	/10
		110	/12
		111	/14
SPRU791D–November 2004–Revised October 2007					Registers	95

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Texas Instruments 28xxx manual 4. Time-Base Control Register TBCTL Field Descriptions, Time-Base Submodule Registers

Contents

TMS320x28xx, 28xxx Enhanced Pulse Width Modulator ePWM Module Reference GuideSubmit Documentation Feedback SPRU791D-November 2004-Revised OctoberContents Controlling Multiple Half H-Bridge HHB Converters List of Figures List of FiguresEvent-Trigger SOCB Pulse Generator List of Tables Submit Documentation Feedback SPRU791D-November 2004-Revised OctoberData Manuals Read This FirstPreface Related Documentation From Texas InstrumentsRelated Documentation From Texas Instruments Tools GuidesApplication Reports TMS320C28x, C28x are trademarks of Texas Instruments TrademarksSubmit Documentation Feedback SPRU791D-November 2004-Revised OctoberSubmodule Overview IntroductionChapter Introduction1.2 Submodule Overview 1.1 IntroductionSubmodule Overview Figure 1-1. Multiple ePWM Modules∙ ADC start-of-conversion signals EPWMxSOCA and EPWMxSOCB Figure 1-2. Submodules and Signal Connections for an ePWM Module∙ PWM output signals EPWMxA and EPWMxB ∙ Trip-zone signals TZ1 to TZ6Register Mapping 1.3 Register MappingSubmit Documentation Feedback Register MappingOffset Counter-Compare CC Submodule ePWM SubmodulesOverview Time-Base TB SubmoduleSubmit Documentation Feedback Table 2-1. Submodule Configuration Parameters2.1 Overview OverviewSubmit Documentation Feedback Table 2-1. Submodule Configuration Parameters continuedExample 2-1. Constant Definitions Used in the Code Examples OverviewSubmit Documentation Feedback Example 2-1. Constant Definitions Used in the Code Examples continuedOverview 2.2.1 Purpose of the Time-Base Submodule Figure 2-1. Time-Base Submodule Block Diagram2.2 Time-Base TB Submodule Table 2-2. Time-Base Submodule Registers Figure 2-2. Time-Base Submodule Signals and Registers2.2.2 Controlling and Monitoring the Time-base Submodule ∙ Up-Count Mode Table 2-3. Key Time-Base Signals2.2.3 Calculating PWM Period and Frequency ∙ Up-Down-Count Mode∙ Shadow Register Figure 2-3. Time-Base Frequency and Period2.2.3.1 Time-Base Period Shadow Register ∙ Active RegisterFigure 2-4. Time-Base Counter Synchronization Scheme 2.2.3.2 Time-Base Counter SynchronizationFigure 2-5. Time-Base Counter Synchronization Scheme ∙ Software Forced Synchronization Pulse Figure 2-6. Time-Base Counter Synchronization Scheme∙ EPWMxSYNCI Synchronization Input Pulse Figure 2-7. Time-Base Up-Count Mode Waveforms 2.2.4 Phase Locking the Time-Base Clocks of Multiple ePWM Modules2.2.5 Time-base Counter Modes and Timing Waveforms Time-Base TB Submodule Figure 2-8. Time-Base Down-Count Mode WaveformsEvent Figure 2-11. Counter-Compare Submodule 2.3 Counter-Compare CC SubmoduleEvent Figure 2-11 illustrates the counter-compare submodule within the ePWMFigure 2-12. Detailed View of the Counter-Compare Submodule 2.3.1 Purpose of the Counter-Compare Submodule2.3.2 Controlling and Monitoring the Counter-Compare Submodule Table 2-4. Counter-Compare Submodule Registers∙ Shadow Mode Table 2-5. Counter-Compare Submodule Key Signals2.3.3 Operational Highlights for the Counter-Compare Submodule 2.3.4 Count Mode Timing WaveformsCounter-Compare CC Submodule ∙ Up-down-count mode used to generate a symmetrical PWM waveformFigure 2-13. Counter-Compare Event Waveforms in Up-Count Mode Figure 2-14. Counter-Compare Events in Down-Count ModeSynchronization Event Synchronization EventTable 2-6. Action-Qualifier Submodule Registers 2.4 Action-Qualifier AQ Submodule2.4.1 Purpose of the Action-Qualifier Submodule Figure 2-17. Action-Qualifier Submodule∙ Clear Low Figure 2-18. Action-Qualifier Submodule Inputs and OutputsTable 2-7. Action-Qualifier Submodule Possible Input Events ∙ Set HighPage Table 2-10. Action-Qualifier Event Priority for Down-Count Mode 2.4.3 Action-Qualifier Event PriorityTable 2-8. Action-Qualifier Event Priority for Up-Down-Count Mode Table 2-9. Action-Qualifier Event Priority for Up-Count ModeTable 2-11. Behavior if CMPA/CMPB is Greater than the Period 2.4.4 Waveforms for Common ConfigurationsWhen using up-count mode to generate an asymmetric PWM See the Using Enhanced Pulse Width Modulator ePWM Module for 0-100%Figure 2-20. Up-Down-Count Mode Symmetrical Waveform Action-Qualifier AQ Submodule EPWMxB-Active HighExample 2-2. Code Sample for Figure Action-Qualifier AQ Submodule EPWMxB-Active LowSubmit Documentation Feedback Example 2-3. Code Sample for FigureEPWMxA Action-Qualifier AQ SubmoduleSubmit Documentation Feedback Example 2-4. Code Sample for FigureAction-Qualifier AQ Submodule Action-Qualifier AQ Submodule EPWMxA and EPWMxB - Active LowExample 2-5. Code Sample for Figure Action-Qualifier AQ Submodule EPWMxA and EPWMxB - ComplementaryExample 2-6. Code Sample for Figure Submit Documentation Feedback EPWMxA-Active LowExample 2-7. Code Sample for Figure Action-Qualifier AQ SubmoduleFigure 2-27. DeadBand Submodule 2.5 Dead-Band Generator DB Submodule2.5.1 Purpose of the Dead-Band Submodule 2.5.2 Controlling and Monitoring the Dead-Band Submodule∙ Input Source Selection Figure 2-28. Configuration Options for the Dead-Band Submodule∙ Mode 2-5 Classical Dead-Band Polarity Settings 2.5.3 Operational Highlights for the Dead-Band SubmoduleSubmit Documentation Feedback action-qualifier submodule to generate the signal as shown for EPWMxATable 2-13. Classical Dead-Band Operating Modes Dead-Band Generator DB SubmoduleSubmit Documentation Feedback Figure 2-29 shows waveforms for typical cases where 0% duty 100%Figure 2-29. Dead-Band Waveforms for Typical Cases 0% Duty 100% Dead-Band Generator DB SubmoduleFED = DBFED × TTBCLK RED = DBRED × TTBCLK 2.6.3 Operational Highlights for the PWM-Chopper Submodule 2.6 PWM-Chopper PC Submodule2.6.1 Purpose of the PWM-Chopper Submodule 2.6.2 Controlling the PWM-Chopper SubmodulePWM-Chopper PC Submodule 2.6.4 WaveformsFigure 2-31. PWM-Chopper Submodule Operational Details Start OSHT pulse EPWMxA in PSCLK Prog. pulse width OSHTWTH OSHT 2.6.4.1 One-Shot PulsePulses Table 2-16. Possible Pulse Width Values for SYSCLKOUT = 100 MHzPSCLK Period 2.6.4.2 Duty Cycle ControlSustaining Pulses 87.5%Figure 2-35. Trip-Zone Submodule 2.7 Trip-Zone TZ Submodule2.7.1 Purpose of the Trip-Zone Submodule ∙ Cycle-by-Cycle CBC 2.7.2 Controlling and Monitoring the Trip-Zone Submodule2.7.3 Operational Highlights for the Trip-Zone Submodule Table 2-17. Trip-Zone Submodule RegistersScenario B Example 2-8. Trip-Zone ConfigurationsTable 2-18. Possible Actions On a Trip Event Scenario ATrip-Zone TZ Submodule 2.7.4 Generating Trip Event InterruptsFigure 2-36. Trip-Zone Submodule Mode Control Logic Figure 2-38. Event-Trigger Submodule 2.8 Event-Trigger ET SubmoduleFigure 2-37. Trip-Zone Submodule Interrupt Logic 2.8.1 Operational Overview of the Event-Trigger Submodule SignalsTable 2-19. Event-Trigger Submodule Registers input = Figure 2-41. Event-Trigger Interrupt GeneratorSubmit Documentation Feedback Figure 2-42. Event-Trigger SOCA Pulse GeneratorFigure 2-43. Event-Trigger SOCB Pulse Generator Event-Trigger ET SubmoduleSubmit Documentation Feedback SPRU791D-November 2004-Revised OctoberFrequencies Applications to Power TopologiesKey Configuration Capabilities Overview of Multiple ModulesFigure 3-1. Simplified ePWM Module 3.2 Key Configuration Capabilities3.1 Overview of Multiple Modules Controlling Multiple Buck Converters With Independent Frequencies 3.3 Controlling Multiple Buck Converters With Independent FrequenciesSubmit Documentation Feedback Controlling Multiple Buck Converters With Independent FrequenciesIndicates this event triggers an ADC start Controlling Multiple Buck Converters With Independent FrequenciesSubmit Documentation Feedback Example 3-1. Configuration for Example in FigureControlling Multiple Buck Converters With Independent Frequencies Figure 3-5. Control of Four Buck Stages. Note FPWM2 = N x FPWM1 3.4 Controlling Multiple Buck Converters With Same FrequenciesControlling Multiple Buck Converters With Same Frequencies Figure 3-6. Buck Waveforms for Figure 3-5 Note FPWM2 = FPWM1Submit Documentation Feedback Example 3-2. Code Snippet for Configuration in FigureControlling Multiple Buck Converters With Same Frequencies Figure 3-7. Control of Two Half-H Bridge Stages FPWM2 = N x FPWM1 3.5 Controlling Multiple Half H-Bridge HHB ConvertersControlling Multiple Half H-Bridge HHB Converters Example 3-3. Code Snippet for Configuration in Figure 3.6 Controlling Dual 3-Phase Inverters for Motors ACI and PMSMSubmit Documentation Feedback Controlling Dual 3-Phase Inverters for Motors ACI and PMSMControlling Dual 3-Phase Inverters for Motors ACI and PMSM Submit Documentation Feedback Example 3-4. Code Snippet for Configuration in FigureControlling Dual 3-Phase Inverters for Motors ACI and PMSM Figure 3-11. Configuring Two PWM Modules for Phase Control 3.7 Practical Applications Using Phase Control Between PWM Modules3.8 Controlling a 3-Phase Interleaved DC/DC Converter =240 Figure 3-13. Control of a 3-Phase Interleaved DC/DC ConverterControlling a 3-Phase Interleaved DC/DC Converter Controlling a 3-Phase Interleaved DC/DC Converter Figure 3-14. 3-Phase Interleaved DC/DC Converter Waveforms for FigureSubmit Documentation Feedback Example 3-5. Code Snippet for Configuration in FigureControlling a 3-Phase Interleaved DC/DC Converter Figure 3-15. Controlling a Full-H Bridge Stage FPWM2 = FPWM1 3.9 Controlling Zero Voltage Switched Full Bridge ZVSFB ConverterFigure 3-16. ZVS Full-H Bridge Waveforms Controlling Zero Voltage Switched Full Bridge ZVSFB ConverterSubmit Documentation Feedback Example 3-6. Code Snippet for Configuration in FigureControlling Zero Voltage Switched Full Bridge ZVSFB Converter Submit Documentation Feedback SPRU791D-November 2004-Revised OctoberAction-Qualifier Submodule Registers RegistersTime-Base Submodule Registers Counter-Compare Submodule RegistersFigure 4-1. Time-Base Period Register TBPRD Figure 4-2. Time-Base Phase Register TBPHSTable 4-2. Time-Base Phase Register TBPHS Field Descriptions 4.1 Time-Base Submodule RegistersSubmit Documentation Feedback Figure 4-4. Time-Base Control Register TBCTLTable 4-4. Time-Base Control Register TBCTL Field Descriptions Time-Base Submodule RegistersSubmit Documentation Feedback Time-Base Submodule RegistersFigure 4-6. Counter-Compare A Register CMPA 4.2 Counter-Compare Submodule RegistersFigure 4-5. Time-Base Status Register TBSTS Table 4-5. Time-Base Status Register TBSTS Field DescriptionsCounter-Compare Submodule Registers Table 4-6. Counter-Compare A Register CMPA Field DescriptionsFigure 4-7. Counter-Compare B Register CMPB Table 4-7. Counter-Compare B Register CMPB Field DescriptionsAction-Qualifier Submodule Registers 4.3 Action-Qualifier Submodule RegistersFigure 4-8. Counter-Compare Control Register CMPCTL Table 4-8. Counter-Compare Control Register CMPCTL Field DescriptionsSubmit Documentation Feedback Figure 4-9. Action-Qualifier Output A Control Register AQCTLAAction-Qualifier Submodule Registers Submit Documentation Feedback Figure 4-10. Action-Qualifier Output B Control Register AQCTLBAction-Qualifier Submodule Registers Figure 4-11. Action-Qualifier Software Force Register AQSFRC Submit Documentation Feedback 4.4 Dead-Band Submodule RegistersFigure 4-13. Dead-Band Generator Control Register DBCTL Dead-Band Submodule RegistersSubmit Documentation Feedback Dead-Band Submodule RegistersFigure 4-16. PWM-Chopper Control Register PCCTL Figure 4-14. Dead-Band Generator Rising Edge Delay Register DBREDFigure 4-15. Dead-Band Generator Falling Edge Delay Register DBFED 4.5 PWM-Chopper Submodule Control RegisterSubmit Documentation Feedback 4.6 Trip-Zone Submodule Control and Status RegistersPWM-Chopper Control Register PCCTL Bit Descriptions continued Trip-Zone Submodule Control and Status RegistersSubmit Documentation Feedback Figure 4-17. Trip-Zone Select Register TZSELTrip-Zone Submodule Control and Status Registers Trip-Zone Submodule Control and Status Registers Figure 4-19. Trip-Zone Enable Interrupt Register TZEINTFigure 4-18. Trip-Zone Control Register TZCTL Table 4-18. Trip-Zone Control Register TZCTL Field DescriptionsSubmit Documentation Feedback Figure 4-20. Trip-Zone Flag Register TZFLGTable 4-20. Trip-Zone Flag Register TZFLG Field Descriptions Trip-Zone Submodule Control and Status RegistersFigure 4-22. Trip-Zone Force Register TZFRC 4.7 Event-Trigger Submodule RegistersFigure 4-21. Trip-Zone Clear Register TZCLR Table 4-21. Trip-Zone Clear Register TZCLR Field DescriptionsName Figure 4-23. Event-Trigger Selection Register ETSELTable 4-23. Event-Trigger Selection Register ETSEL Field Descriptions BitsSubmit Documentation Feedback Figure 4-24. Event-Trigger Prescale Register ETPSTable 4-24. Event-Trigger Prescale Register ETPS Field Descriptions Event-Trigger Submodule RegistersSubmit Documentation Feedback Figure 4-25. Event-Trigger Flag Register ETFLGName DescriptionEvent-Trigger Submodule Registers Table 4-25. Event-Trigger Flag Register ETFLG Field DescriptionsFigure 4-26. Event-Trigger Clear Register ETCLR Table 4-26. Event-Trigger Clear Register ETCLR Field DescriptionsTable 4-27. Event-Trigger Force Register ETFRC Field Descriptions 4.8 Proper Interrupt Initialization ProcedureProper Interrupt Initialization Procedure Figure 4-27. Event-Trigger Force Register ETFRCSubmit Documentation Feedback SPRU791D-November 2004-Revised OctoberSPRU791D-November 2004-Revised October Revision HistoryAppendix A Table A-1. Changes for Revision DSubmit Documentation Feedback Table A-1. Changes for Revision D continuedAppendix A SectionApplications power.ti.comIMPORTANT NOTICE Products