Texas Instruments 28xxx, TMS320x28xx manual Example 3-4. Code Snippet for Configuration in Figure

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Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM)

Example 3-4. Code Snippet for Configuration in Figure 3-9

//=====================================================================

//Configuration //=====================================================================

//Initialization Time

//========================// EPWM Module 1 config
EPwm1Regs.TBPRD = 800;	//	Period = 1600 TBCLK counts
EPwm1Regs.TBPHS = 0;	//	Set Phase register to zero
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;//		Symmetrical mode
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;	//	Master module
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;	//	Sync down-stream module
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; //		load on CTR=Zero
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; //		load on CTR=Zero
EPwm1Regs.AQCTLA.bit.CAU = AQ_SET;	//	set actions for EPWM1A
EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR;
EPwm1Regs.DBCTL.bit.MODE = DB_FULL_ENABLE;	//	enable Dead-band module
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;	//	Active Hi complementary
EPwm1Regs.DBFED = 50;	//	FED = 50 TBCLKs
EPwm1Regs.DBRED = 50;	//	RED = 50 TBCLKs
// EPWM Module 2 config
EPwm2Regs.TBPRD = 800;	//	Period = 1600 TBCLK counts
EPwm2Regs.TBPHS = 0;	//	Set Phase register to zero
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Symmetrical mode
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE;	//	Slave module
EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;	//	sync flow-through
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; //		load on CTR=Zero
EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; //		load on CTR=Zero
EPwm2Regs.AQCTLA.bit.CAU = AQ_SET;	//	set actions for EPWM2A
EPwm2Regs.AQCTLA.bit.CAD = AQ_CLEAR;
EPwm2Regs.DBCTL.bit.MODE = DB_FULL_ENABLE;	//	enable Dead-band module
EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;	//	Active Hi complementary
EPwm2Regs.DBFED = 50; // FED = 50 TBCLKs
EPwm2Regs.DBRED = 50; // RED = 50 TBCLKs
// EPWM Module 3 config
EPwm3Regs.TBPRD = 800;	//	Period = 1600 TBCLK counts
EPwm3Regs.TBPHS = 0;	//	Set Phase register to zero
EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;//		Symmetrical mode
EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE;	//	Slave module
EPwm3Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;	//	sync flow-through
EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; //		load on CTR=Zero
EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; //		load on CTR=Zero
EPwm3Regs.AQCTLA.bit.CAU = AQ_SET;	//	set actions for EPWM3A
EPwm3Regs.AQCTLA.bit.CAD = AQ_CLEAR;
EPwm3Regs.DBCTL.bit.MODE = DB_FULL_ENABLE;	//	enable Dead-band module
EPwm3Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;	//	Active Hi complementary
EPwm3Regs.DBFED = 50; // FED = 50 TBCLKs
EPwm3Regs.DBRED = 50; // RED = 50 TBCLKs

//Run Time (Note: Example execution of one run-time instant) //========================================================= EPwm1Regs.CMPA.half.CMPA = 500; // adjust duty for output EPWM1A EPwm2Regs.CMPA.half.CMPA = 600; // adjust duty for output EPWM2A EPwm3Regs.CMPA.half.CMPA = 700; // adjust duty for output EPWM3A

SPRU791D–November 2004–Revised October 2007 Applications to Power Topologies 83

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