Manuals / Texas Instruments / Computer Equipment / Network Router

Texas Instruments TMS320x28xx, 28xxx Dead-Band Submodule Registers, Submit Documentation Feedback

Models: 28xxx TMS320x28xx

1 119

Download 119 pages 2.85 Kb

Page 104

Manual background

www.ti.com

Dead-Band Submodule Registers

Table 4-13. Dead-Band Generator Control Register (DBCTL) Field Descriptions

Bits	Name	Value	Description
15-6	Reserved		Reserved
5-4	IN_MODE		Dead Band Input Mode Control
			Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown in Figure 2-28.
			This allows you to select the input source to the falling-edge and rising-edge delay.
			To produce classical dead-band waveforms the default is EPWMxA In is the source for both
			falling and rising-edge delays.
		00	EPWMxA In (from the action-qualifier) is the source for both falling-edge and rising-edge
			delay.
		01	EPWMxB In (from the action-qualifier) is the source for rising-edge delayed signal.
			EPWMxA In (from the action-qualifier) is the source for falling-edge delayed signal.
		10	EPWMxA In (from the action-qualifier) is the source for rising-edge delayed signal.
			EPWMxB In (from the action-qualifier) is the source for falling-edge delayed signal.
		11	EPWMxB In (from the action-qualifier) is the source for both rising-edge delay and
			falling-edge delayed signal.
3-2	POLSEL		Polarity Select Control
			Bit 3 controls the S3 switch and bit 2 controls the S2 switch shown in Figure 2-28.
			This allows you to selectively invert one of the delayed signals before it is sent out of the
			dead-band submodule.
			The following descriptions correspond to classical upper/lower switch control as found in one
			leg of a digital motor control inverter.
			These assume that DBCTL[OUT_MODE] = 1,1 and DBCTL[IN_MODE] = 0,0. Other
			enhanced modes are also possible, but not regarded as typical usage modes.
		00	Active high (AH) mode. Neither EPWMxA nor EPWMxB is inverted (default).
		01	Active low complementary (ALC) mode. EPWMxA is inverted.
		10	Active high complementary (AHC). EPWMxB is inverted.
		11	Active low (AL) mode. Both EPWMxA and EPWMxB are inverted.
1-0	OUT_MODE		Dead-band Output Mode Control
			Bit 1 controls the S1 switch and bit 0 controls the S0 switch shown in Figure 2-28.
			This allows you to selectively enable or bypass the dead-band generation for the falling-edge
			and rising-edge delay.
		00	Dead-band generation is bypassed for both output signals. In this mode, both the EPWMxA
			and EPWMxB output signals from the action-qualifier are passed directly to the PWM-chopper
			submodule.
			In this mode, the POLSEL and IN_MODE bits have no effect.
		01	Disable rising-edge delay. The EPWMxA signal from the action-qualifier is passed straight
			through to the EPWMxA input of the PWM-chopper submodule.
			The falling-edge delayed signal is seen on output EPWMxB. The input signal for the delay is
			determined by DBCTL[IN_MODE].
		10	The rising-edge delayed signal is seen on output EPWMxA. The input signal for the delay is
			determined by DBCTL[IN_MODE].
			Disable falling-edge delay. The EPWMxB signal from the action-qualifier is passed straight
			through to the EPWMxB input of the PWM-chopper submodule.
		11	Dead-band is fully enabled for both rising-edge delay on output EPWMxA and falling-edge
			delay on output EPWMxB. The input signal for the delay is determined by DBCTL[IN_MODE].

104

Registers

SPRU791D–November 2004–Revised October 2007

Submit Documentation Feedback

Image 104

Texas Instruments TMS320x28xx, 28xxx manual Dead-Band Submodule Registers, Submit Documentation Feedback

Contents

Reference Guide TMS320x28xx, 28xxx Enhanced Pulse Width Modulator ePWM ModuleSPRU791D-November 2004-Revised October Submit Documentation FeedbackContents Controlling Multiple Half H-Bridge HHB Converters List of Figures List of FiguresEvent-Trigger SOCB Pulse Generator List of Tables SPRU791D-November 2004-Revised October Submit Documentation FeedbackRead This First PrefaceRelated Documentation From Texas Instruments Data ManualsRelated Documentation From Texas Instruments Tools GuidesApplication Reports Trademarks TMS320C28x, C28x are trademarks of Texas InstrumentsSPRU791D-November 2004-Revised October Submit Documentation FeedbackIntroduction ChapterIntroduction Submodule Overview1.1 Introduction 1.2 Submodule OverviewFigure 1-1. Multiple ePWM Modules Submodule OverviewFigure 1-2. Submodules and Signal Connections for an ePWM Module ∙ PWM output signals EPWMxA and EPWMxB∙ Trip-zone signals TZ1 to TZ6 ∙ ADC start-of-conversion signals EPWMxSOCA and EPWMxSOCB1.3 Register Mapping Register MappingSubmit Documentation Feedback Register MappingOffset ePWM Submodules OverviewTime-Base TB Submodule Counter-Compare CC SubmoduleTable 2-1. Submodule Configuration Parameters 2.1 OverviewOverview Submit Documentation FeedbackTable 2-1. Submodule Configuration Parameters continued Example 2-1. Constant Definitions Used in the Code ExamplesOverview Submit Documentation FeedbackSubmit Documentation Feedback Example 2-1. Constant Definitions Used in the Code Examples continuedOverview 2.2.1 Purpose of the Time-Base Submodule Figure 2-1. Time-Base Submodule Block Diagram2.2 Time-Base TB Submodule Table 2-2. Time-Base Submodule Registers Figure 2-2. Time-Base Submodule Signals and Registers2.2.2 Controlling and Monitoring the Time-base Submodule Table 2-3. Key Time-Base Signals 2.2.3 Calculating PWM Period and Frequency∙ Up-Down-Count Mode ∙ Up-Count ModeFigure 2-3. Time-Base Frequency and Period 2.2.3.1 Time-Base Period Shadow Register∙ Active Register ∙ Shadow Register2.2.3.2 Time-Base Counter Synchronization Figure 2-4. Time-Base Counter Synchronization SchemeFigure 2-5. Time-Base Counter Synchronization Scheme ∙ Software Forced Synchronization Pulse Figure 2-6. Time-Base Counter Synchronization Scheme∙ EPWMxSYNCI Synchronization Input Pulse Figure 2-7. Time-Base Up-Count Mode Waveforms 2.2.4 Phase Locking the Time-Base Clocks of Multiple ePWM Modules2.2.5 Time-base Counter Modes and Timing Waveforms Time-Base TB Submodule Figure 2-8. Time-Base Down-Count Mode WaveformsEvent 2.3 Counter-Compare CC Submodule EventFigure 2-11 illustrates the counter-compare submodule within the ePWM Figure 2-11. Counter-Compare Submodule2.3.1 Purpose of the Counter-Compare Submodule 2.3.2 Controlling and Monitoring the Counter-Compare SubmoduleTable 2-4. Counter-Compare Submodule Registers Figure 2-12. Detailed View of the Counter-Compare SubmoduleTable 2-5. Counter-Compare Submodule Key Signals 2.3.3 Operational Highlights for the Counter-Compare Submodule2.3.4 Count Mode Timing Waveforms ∙ Shadow Mode∙ Up-down-count mode used to generate a symmetrical PWM waveform Figure 2-13. Counter-Compare Event Waveforms in Up-Count ModeFigure 2-14. Counter-Compare Events in Down-Count Mode Counter-Compare CC SubmoduleSynchronization Event Synchronization Event2.4 Action-Qualifier AQ Submodule 2.4.1 Purpose of the Action-Qualifier SubmoduleFigure 2-17. Action-Qualifier Submodule Table 2-6. Action-Qualifier Submodule RegistersFigure 2-18. Action-Qualifier Submodule Inputs and Outputs Table 2-7. Action-Qualifier Submodule Possible Input Events∙ Set High ∙ Clear LowPage 2.4.3 Action-Qualifier Event Priority Table 2-8. Action-Qualifier Event Priority for Up-Down-Count ModeTable 2-9. Action-Qualifier Event Priority for Up-Count Mode Table 2-10. Action-Qualifier Event Priority for Down-Count Mode2.4.4 Waveforms for Common Configurations When using up-count mode to generate an asymmetric PWMSee the Using Enhanced Pulse Width Modulator ePWM Module for 0-100% Table 2-11. Behavior if CMPA/CMPB is Greater than the PeriodFigure 2-20. Up-Down-Count Mode Symmetrical Waveform Action-Qualifier AQ Submodule EPWMxB-Active HighExample 2-2. Code Sample for Figure EPWMxB-Active Low Action-Qualifier AQ SubmoduleExample 2-3. Code Sample for Figure EPWMxAAction-Qualifier AQ Submodule Submit Documentation FeedbackSubmit Documentation Feedback Example 2-4. Code Sample for FigureAction-Qualifier AQ Submodule Action-Qualifier AQ Submodule EPWMxA and EPWMxB - Active LowExample 2-5. Code Sample for Figure Action-Qualifier AQ Submodule EPWMxA and EPWMxB - ComplementaryExample 2-6. Code Sample for Figure EPWMxA-Active Low Example 2-7. Code Sample for FigureAction-Qualifier AQ Submodule Submit Documentation Feedback2.5 Dead-Band Generator DB Submodule 2.5.1 Purpose of the Dead-Band Submodule2.5.2 Controlling and Monitoring the Dead-Band Submodule Figure 2-27. DeadBand SubmoduleFigure 2-28. Configuration Options for the Dead-Band Submodule ∙ Mode 2-5 Classical Dead-Band Polarity Settings2.5.3 Operational Highlights for the Dead-Band Submodule ∙ Input Source Selectionaction-qualifier submodule to generate the signal as shown for EPWMxA Table 2-13. Classical Dead-Band Operating ModesDead-Band Generator DB Submodule Submit Documentation FeedbackFigure 2-29 shows waveforms for typical cases where 0% duty 100% Figure 2-29. Dead-Band Waveforms for Typical Cases 0% Duty 100%Dead-Band Generator DB Submodule Submit Documentation FeedbackFED = DBFED × TTBCLK RED = DBRED × TTBCLK 2.6 PWM-Chopper PC Submodule 2.6.1 Purpose of the PWM-Chopper Submodule2.6.2 Controlling the PWM-Chopper Submodule 2.6.3 Operational Highlights for the PWM-Chopper SubmodulePWM-Chopper PC Submodule 2.6.4 WaveformsFigure 2-31. PWM-Chopper Submodule Operational Details 2.6.4.1 One-Shot Pulse PulsesTable 2-16. Possible Pulse Width Values for SYSCLKOUT = 100 MHz Start OSHT pulse EPWMxA in PSCLK Prog. pulse width OSHTWTH OSHT2.6.4.2 Duty Cycle Control Sustaining Pulses87.5% PSCLK PeriodFigure 2-35. Trip-Zone Submodule 2.7 Trip-Zone TZ Submodule2.7.1 Purpose of the Trip-Zone Submodule 2.7.2 Controlling and Monitoring the Trip-Zone Submodule 2.7.3 Operational Highlights for the Trip-Zone SubmoduleTable 2-17. Trip-Zone Submodule Registers ∙ Cycle-by-Cycle CBCExample 2-8. Trip-Zone Configurations Table 2-18. Possible Actions On a Trip EventScenario A Scenario BTrip-Zone TZ Submodule 2.7.4 Generating Trip Event InterruptsFigure 2-36. Trip-Zone Submodule Mode Control Logic Figure 2-38. Event-Trigger Submodule 2.8 Event-Trigger ET SubmoduleFigure 2-37. Trip-Zone Submodule Interrupt Logic Signals 2.8.1 Operational Overview of the Event-Trigger SubmoduleTable 2-19. Event-Trigger Submodule Registers Figure 2-41. Event-Trigger Interrupt Generator input =Figure 2-42. Event-Trigger SOCA Pulse Generator Figure 2-43. Event-Trigger SOCB Pulse GeneratorEvent-Trigger ET Submodule Submit Documentation FeedbackSPRU791D-November 2004-Revised October Submit Documentation FeedbackApplications to Power Topologies Key Configuration CapabilitiesOverview of Multiple Modules FrequenciesFigure 3-1. Simplified ePWM Module 3.2 Key Configuration Capabilities3.1 Overview of Multiple Modules 3.3 Controlling Multiple Buck Converters With Independent Frequencies Controlling Multiple Buck Converters With Independent FrequenciesControlling Multiple Buck Converters With Independent Frequencies Submit Documentation FeedbackControlling Multiple Buck Converters With Independent Frequencies Indicates this event triggers an ADC startSubmit Documentation Feedback Example 3-1. Configuration for Example in FigureControlling Multiple Buck Converters With Independent Frequencies 3.4 Controlling Multiple Buck Converters With Same Frequencies Figure 3-5. Control of Four Buck Stages. Note FPWM2 = N x FPWM1Figure 3-6. Buck Waveforms for Figure 3-5 Note FPWM2 = FPWM1 Controlling Multiple Buck Converters With Same FrequenciesSubmit Documentation Feedback Example 3-2. Code Snippet for Configuration in FigureControlling Multiple Buck Converters With Same Frequencies 3.5 Controlling Multiple Half H-Bridge HHB Converters Figure 3-7. Control of Two Half-H Bridge Stages FPWM2 = N x FPWM1Controlling Multiple Half H-Bridge HHB Converters 3.6 Controlling Dual 3-Phase Inverters for Motors ACI and PMSM Example 3-3. Code Snippet for Configuration in FigureControlling Dual 3-Phase Inverters for Motors ACI and PMSM Submit Documentation FeedbackControlling Dual 3-Phase Inverters for Motors ACI and PMSM Submit Documentation Feedback Example 3-4. Code Snippet for Configuration in FigureControlling Dual 3-Phase Inverters for Motors ACI and PMSM 3.7 Practical Applications Using Phase Control Between PWM Modules Figure 3-11. Configuring Two PWM Modules for Phase Control3.8 Controlling a 3-Phase Interleaved DC/DC Converter =240 Figure 3-13. Control of a 3-Phase Interleaved DC/DC ConverterControlling a 3-Phase Interleaved DC/DC Converter Figure 3-14. 3-Phase Interleaved DC/DC Converter Waveforms for Figure Controlling a 3-Phase Interleaved DC/DC ConverterSubmit Documentation Feedback Example 3-5. Code Snippet for Configuration in FigureControlling a 3-Phase Interleaved DC/DC Converter 3.9 Controlling Zero Voltage Switched Full Bridge ZVSFB Converter Figure 3-15. Controlling a Full-H Bridge Stage FPWM2 = FPWM1Controlling Zero Voltage Switched Full Bridge ZVSFB Converter Figure 3-16. ZVS Full-H Bridge WaveformsSubmit Documentation Feedback Example 3-6. Code Snippet for Configuration in FigureControlling Zero Voltage Switched Full Bridge ZVSFB Converter SPRU791D-November 2004-Revised October Submit Documentation FeedbackRegisters Time-Base Submodule RegistersCounter-Compare Submodule Registers Action-Qualifier Submodule RegistersFigure 4-2. Time-Base Phase Register TBPHS Table 4-2. Time-Base Phase Register TBPHS Field Descriptions4.1 Time-Base Submodule Registers Figure 4-1. Time-Base Period Register TBPRDFigure 4-4. Time-Base Control Register TBCTL Table 4-4. Time-Base Control Register TBCTL Field DescriptionsTime-Base Submodule Registers Submit Documentation FeedbackTime-Base Submodule Registers Submit Documentation Feedback4.2 Counter-Compare Submodule Registers Figure 4-5. Time-Base Status Register TBSTSTable 4-5. Time-Base Status Register TBSTS Field Descriptions Figure 4-6. Counter-Compare A Register CMPATable 4-6. Counter-Compare A Register CMPA Field Descriptions Figure 4-7. Counter-Compare B Register CMPBTable 4-7. Counter-Compare B Register CMPB Field Descriptions Counter-Compare Submodule Registers4.3 Action-Qualifier Submodule Registers Figure 4-8. Counter-Compare Control Register CMPCTLTable 4-8. Counter-Compare Control Register CMPCTL Field Descriptions Action-Qualifier Submodule RegistersSubmit Documentation Feedback Figure 4-9. Action-Qualifier Output A Control Register AQCTLAAction-Qualifier Submodule Registers Submit Documentation Feedback Figure 4-10. Action-Qualifier Output B Control Register AQCTLBAction-Qualifier Submodule Registers Figure 4-11. Action-Qualifier Software Force Register AQSFRC 4.4 Dead-Band Submodule Registers Figure 4-13. Dead-Band Generator Control Register DBCTLDead-Band Submodule Registers Submit Documentation FeedbackDead-Band Submodule Registers Submit Documentation FeedbackFigure 4-14. Dead-Band Generator Rising Edge Delay Register DBRED Figure 4-15. Dead-Band Generator Falling Edge Delay Register DBFED4.5 PWM-Chopper Submodule Control Register Figure 4-16. PWM-Chopper Control Register PCCTL4.6 Trip-Zone Submodule Control and Status Registers PWM-Chopper Control Register PCCTL Bit Descriptions continuedTrip-Zone Submodule Control and Status Registers Submit Documentation FeedbackSubmit Documentation Feedback Figure 4-17. Trip-Zone Select Register TZSELTrip-Zone Submodule Control and Status Registers Figure 4-19. Trip-Zone Enable Interrupt Register TZEINT Figure 4-18. Trip-Zone Control Register TZCTLTable 4-18. Trip-Zone Control Register TZCTL Field Descriptions Trip-Zone Submodule Control and Status RegistersFigure 4-20. Trip-Zone Flag Register TZFLG Table 4-20. Trip-Zone Flag Register TZFLG Field DescriptionsTrip-Zone Submodule Control and Status Registers Submit Documentation Feedback4.7 Event-Trigger Submodule Registers Figure 4-21. Trip-Zone Clear Register TZCLRTable 4-21. Trip-Zone Clear Register TZCLR Field Descriptions Figure 4-22. Trip-Zone Force Register TZFRCFigure 4-23. Event-Trigger Selection Register ETSEL Table 4-23. Event-Trigger Selection Register ETSEL Field DescriptionsBits NameFigure 4-24. Event-Trigger Prescale Register ETPS Table 4-24. Event-Trigger Prescale Register ETPS Field DescriptionsEvent-Trigger Submodule Registers Submit Documentation FeedbackFigure 4-25. Event-Trigger Flag Register ETFLG NameDescription Submit Documentation FeedbackTable 4-25. Event-Trigger Flag Register ETFLG Field Descriptions Figure 4-26. Event-Trigger Clear Register ETCLRTable 4-26. Event-Trigger Clear Register ETCLR Field Descriptions Event-Trigger Submodule Registers4.8 Proper Interrupt Initialization Procedure Proper Interrupt Initialization ProcedureFigure 4-27. Event-Trigger Force Register ETFRC Table 4-27. Event-Trigger Force Register ETFRC Field DescriptionsSPRU791D-November 2004-Revised October Submit Documentation FeedbackRevision History Appendix ATable A-1. Changes for Revision D SPRU791D-November 2004-Revised OctoberTable A-1. Changes for Revision D continued Appendix ASection Submit Documentation Feedbackpower.ti.com IMPORTANT NOTICEProducts Applications