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Dead-Band Submodule Registers

Table 4-13. Dead-Band Generator Control Register (DBCTL) Field Descriptions

Bits	Name	Value	Description
15-6	Reserved		Reserved
5-4	IN_MODE		Dead Band Input Mode Control
			Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown in Figure 2-28.
			This allows you to select the input source to the falling-edge and rising-edge delay.
			To produce classical dead-band waveforms the default is EPWMxA In is the source for both
			falling and rising-edge delays.
		00	EPWMxA In (from the action-qualifier) is the source for both falling-edge and rising-edge
			delay.
		01	EPWMxB In (from the action-qualifier) is the source for rising-edge delayed signal.
			EPWMxA In (from the action-qualifier) is the source for falling-edge delayed signal.
		10	EPWMxA In (from the action-qualifier) is the source for rising-edge delayed signal.
			EPWMxB In (from the action-qualifier) is the source for falling-edge delayed signal.
		11	EPWMxB In (from the action-qualifier) is the source for both rising-edge delay and
			falling-edge delayed signal.
3-2	POLSEL		Polarity Select Control
			Bit 3 controls the S3 switch and bit 2 controls the S2 switch shown in Figure 2-28.
			This allows you to selectively invert one of the delayed signals before it is sent out of the
			dead-band submodule.
			The following descriptions correspond to classical upper/lower switch control as found in one
			leg of a digital motor control inverter.
			These assume that DBCTL[OUT_MODE] = 1,1 and DBCTL[IN_MODE] = 0,0. Other
			enhanced modes are also possible, but not regarded as typical usage modes.
		00	Active high (AH) mode. Neither EPWMxA nor EPWMxB is inverted (default).
		01	Active low complementary (ALC) mode. EPWMxA is inverted.
		10	Active high complementary (AHC). EPWMxB is inverted.
		11	Active low (AL) mode. Both EPWMxA and EPWMxB are inverted.
1-0	OUT_MODE		Dead-band Output Mode Control
			Bit 1 controls the S1 switch and bit 0 controls the S0 switch shown in Figure 2-28.
			This allows you to selectively enable or bypass the dead-band generation for the falling-edge
			and rising-edge delay.
		00	Dead-band generation is bypassed for both output signals. In this mode, both the EPWMxA
			and EPWMxB output signals from the action-qualifier are passed directly to the PWM-chopper
			submodule.
			In this mode, the POLSEL and IN_MODE bits have no effect.
		01	Disable rising-edge delay. The EPWMxA signal from the action-qualifier is passed straight
			through to the EPWMxA input of the PWM-chopper submodule.
			The falling-edge delayed signal is seen on output EPWMxB. The input signal for the delay is
			determined by DBCTL[IN_MODE].
		10	The rising-edge delayed signal is seen on output EPWMxA. The input signal for the delay is
			determined by DBCTL[IN_MODE].
			Disable falling-edge delay. The EPWMxB signal from the action-qualifier is passed straight
			through to the EPWMxB input of the PWM-chopper submodule.
		11	Dead-band is fully enabled for both rising-edge delay on output EPWMxA and falling-edge
			delay on output EPWMxB. The input signal for the delay is determined by DBCTL[IN_MODE].

104

Registers

SPRU791D–November 2004–Revised October 2007

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Image 104

Texas Instruments TMS320x28xx, 28xxx manual Inmode

Contents

Reference Guide Submit Documentation Feedback Contents Controlling a 3-Phase Interleaved DC/DC Converter List of Figures Event-Trigger Socb Pulse Generator Simplified ePWM Module List of Tables Submit Documentation Feedback Related Documentation From Texas Instruments Data ManualsCPU Users Guides Peripheral Guides Tools Guides Application Reports Trademarks TMS320C28x, C28x are trademarks of Texas Instruments Submit Documentation Feedback Introduction Introduction Submodule Overview Multiple ePWM Modules ∙ PWM output signals EPWMxA and EPWMxB ∙ Trip-zone signals TZ1 to TZ6∙ ADC start-of-conversion signals EPWMxSOCA and EPWMxSOCB ∙ Peripheral Bus EPWM Submodules and Critical Internal Signal Interconnects Register Mapping Offset Size Name DescriptionTime-Base Submodule Registers Counter-Compare Submodule Registers EPWM Submodules Overview Submodule Configuration ParametersSubmodule Configuration Parameter or Option Example 2-1. Constant Definitions Used in the Code Examples Tbup Chpenable Time-Base TB Submodule Purpose of the Time-Base Submodule Register Controlling and Monitoring the Time-base SubmoduleTime-Base Submodule Registers Key Time-Base Signals ∙ Up-Down-Count Mode∙ Up-Count Mode ∙ Down-Count Mode ∙ Time-Base Period Shadow Mode ∙ Time-Base Period Immediate Load ModeTime-Base Period Shadow Register ∙ Active Register Time-Base Counter Synchronization Time-Base Counter Synchronization Scheme EPWM11SYNCI EPWM11SYNCO ∙ EPWMxSYNCI Synchronization Input Pulse ∙ Software Forced Synchronization Pulse Phase Locking the Time-Base Clocks of Multiple ePWM Modules Time-base Counter Modes and Timing Waveforms Time-Base Down-Count Mode Waveforms Counter-Compare CC Submodule 11. Counter-Compare Submodule Purpose of the Counter-Compare Submodule Controlling and Monitoring the Counter-Compare SubmoduleCounter-Compare Submodule Registers Register Name Address Offset Count Mode Timing Waveforms Counter-Compare Submodule Key Signals∙ Shadow Mode ∙ Immediate Load Mode CTR=CMPA CTR=CMPB CTR = Cmpb Action-Qualifier Submodule Registers Action-Qualifier AQ SubmodulePurpose of the Action-Qualifier Submodule Action-Qualifier Submodule Possible Input Events ∙ Set High∙ Clear Low ∙ Toggle TB Counter equals Actions Action-Qualifier Event Priority for Up-Down-Count Mode Action-Qualifier Event Priority for Up-Count Mode10. Action-Qualifier Event Priority for Down-Count Mode Action-Qualifier Event Priority Waveforms for Common Configurations Use up-down-count mode to generate a symmetric PWMUse up-down-count mode to generate an asymmetric PWM When using up-count mode to generate an asymmetric PWM 20. Up-Down-Count Mode Symmetrical Waveform Example 2-2. Code Sample for Figure Tbctr Value EPWMxA EPWMxB Example 2-3. Code Sample for Figure Tbclk = Sysclkout Example 2-4. Code Sample for Figure EdgePosA Example 2-5. Code Sample for Figure Example 2-6. Code Sample for Figure Tbctr Example 2-7. Code Sample for Figure EPWMxA EPWMxB Dead-Band Generator DB Submodule Purpose of the Dead-Band SubmoduleControlling and Monitoring the Dead-Band Submodule 12. Dead-Band Generator Submodule Registers ∙ Output Mode Control Operational Highlights for the Dead-Band Submodule∙ Input Source Selection ∙ Polarity Control Mode Description 13. Classical Dead-Band Operating Modes 29. Dead-Band Waveforms for Typical Cases 0% Duty 100% Dead-Band Delay in μS FED = Dbfed × Ttbclk RED = Dbred × Ttbclk PWM-Chopper PC Submodule Purpose of the PWM-Chopper SubmoduleControlling the PWM-Chopper Submodule Operational Highlights for the PWM-Chopper Submodule Waveforms 31. PWM-Chopper Submodule Operational Details OSHTWTHz One-Shot Pulse16. Possible Pulse Width Values for Sysclkout = 100 MHz Duty Cycle Control Period Trip-Zone TZ Submodule Purpose of the Trip-Zone Submodule Controlling and Monitoring the Trip-Zone Submodule Operational Highlights for the Trip-Zone Submodule17. Trip-Zone Submodule Registers ∙ Cycle-by-Cycle CBC Example 2-8. Trip-Zone Configurations 18. Possible Actions On a Trip EventScenario a Scenario B 36. Trip-Zone Submodule Mode Control Logic Generating Trip Event Interrupts Event-Trigger ET Submodule 37. Trip-Zone Submodule Interrupt Logic Operational Overview of the Event-Trigger Submodule 19. Event-Trigger Submodule Registers CTR=CMPB CTRD=CMPB 41. Event-Trigger Interrupt Generator 42. Event-Trigger Soca Pulse Generator Submit Documentation Feedback Applications to Power Topologies Controlling Multiple Buck Converters With Independent Key Configuration Capabilities Overview of Multiple Modules CTR=0 EPWM1B CTR=CMPB Control of Four Buck Stages. Here FPWM1≠ FPWM2≠ FPWM3≠ FPWM4 Buck Waveforms for -3Note Only three bucks shown here Example 3-1. Configuration for Example in Figure 500 Controlling Multiple Buck Converters With Same Frequencies Control of Four Buck Stages. Note FPWM2 = N x FPWM1 Buck Waveforms for -5Note FPWM2 = FPWM1 Example 3-2. Code Snippet for Configuration in Figure Controlling Multiple Half H-Bridge HHB Converters Control of Two Half-H Bridge Stages FPWM2 = N x FPWM1 Half-H Bridge Waveforms for -7Note Here FPWM2 = FPWM1 Controlling Dual 3-Phase Inverters for Motors ACI and Pmsm Example 3-3. Code Snippet for Configuration in Figure EPWM1A 10 -Phase Inverter Waveforms for -9Only One Inverter Shown Example 3-4. Code Snippet for Configuration in Figure 11. Configuring Two PWM Modules for Phase Control Controlling a 3-Phase Interleaved DC/DC Converter Controlling a 3-Phase Interleaved DC/DC Converter 13. Control of a 3-Phase Interleaved DC/DC Converter 14 -Phase Interleaved DC/DC Converter Waveforms for Figure Example 3-5. Code Snippet for Configuration in Figure 15. Controlling a Full-H Bridge Stage FPWM2 = FPWM1 16. ZVS Full-H Bridge Waveforms Example 3-6. Code Snippet for Configuration in Figure Submit Documentation Feedback Trip-Zone Submodule Control and Status Registers Proper Interrupt Initialization ProcedurePWM-Chopper Submodule Control Register Time-Base Phase Register Tbphs Field Descriptions Time-Base Submodule RegistersTime-Base Period Register Tbprd Field Descriptions Time-Base Counter Register Tbctr Field Descriptions Time-Base Control Register Tbctl Field Descriptions Bit Field Value Description Software Forced Synchronization Pulse Bit Field Counter-Compare Submodule RegistersTime-Base Status Register Tbsts Field Descriptions Bits Name Description Counter-Compare a Register Cmpa Field DescriptionsCounter-Compare B Register Cmpb Field Descriptions Action-Qualifier Submodule Registers Counter-Compare Control Register Cmpctl Field Descriptions CBD CBD CBU CAD CAU PRD ZROBits Name 10. Action-Qualifier Output B Control Register Aqctlb Csfb Csfa Rldcsf Otsfb Actsfb Otsfa ActsfaRldcsf Inmode Polsel Outmode Dead-Band Submodule RegistersCsfb Inmode PWM-Chopper Submodule Control Register 16. PWM-Chopper Control Register Pcctl Bit DescriptionsName Value Description Reserved Chpduty Trip-Zone Submodule Control and Status RegistersPWM-Chopper Control Register Pcctl Bit Descriptions OSHT6 OSHT5 OSHT4 OSHT3 OSHT2 OSHT1 CBC6 CBC5 CBC4 CBC3 CBC2 CBC1OSHT6 CBC6 18. Trip-Zone Control Register Tzctl Field Descriptions TZB TZATZB OST CBC 20. Trip-Zone Flag Register Tzflg Field Descriptions OST CBC INT 22. Trip-Zone Force Register Tzfrc Field Descriptions Event-Trigger Submodule Registers21. Trip-Zone Clear Register Tzclr Field Descriptions 23. Event-Trigger Selection Register Etsel 24. Event-Trigger Prescale Register Etps Field Descriptions Name Description 24. Event-Trigger Prescale Register Etps Field Descriptions Socb Soca Socb 25. Event-Trigger Flag Register Etflg Field Descriptions26. Event-Trigger Clear Register Etclr Field Descriptions Proper Interrupt Initialization Procedure 27. Event-Trigger Force Register Etfrc Field Descriptions 116 Table A-1. Changes for Revision D Location Modifications, Additions, and Deletions Appendix a Important Notice