Chapter 3Signals and Pinout Tables
A-B Connector Signal Descriptions
Table
Signal | Description | I/O | PU/PD | Comment |
AC_RST# | AC ’97/Intel High Definition Audio Reset: This | O 3.3V |
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| signal is the master hardware reset to external codec(s). |
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AC_SYN | AC ’97/Intel High Definition Audio Sync: This signal | O 3.3V |
| AC_SYN |
C | is a 48 kHz fixed rate sample sync to the codec(s). It is |
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| C is a boot |
| also used to encode the stream number. |
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| strap |
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| signal (see |
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| note |
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| below) |
AC_BIT_ | AC ’97 Bit Clock Input: This signal is a 12.288 MHz | I 3.3V |
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CLK | serial data clock generated by the external codec(s). | O 3.3V |
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| This signal has an Intel integrated |
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| Intel High Definition Audio Bit Clock Output: This |
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| signal is a 24.000MHz serial data clock generated by |
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| the Intel High Definition Audio controller (the Intel |
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| down resistor so that AC_BIT_CLK doesn’t float when |
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| an Intel High Definition Audio codec (or no codec) is |
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| connected but the signals are temporarily configured as |
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| AC ’97. |
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AC_SDO | AC ’97/Intel High Definition Audio Serial Data Out: | O 3.3V |
| AC_SDO |
UT | This signal is the serial TDM data output to the |
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| UT is a |
| codec(s). This serial output is |
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| boot strap |
| rate of 48 Mb/s for Intel High Definition Audio. |
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| signal (see |
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| note |
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| below) |
AC_SDIN | AC ’97//Intel High Definition Audio Serial Data In | I 3.3V |
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[2:0] | [0]: These signals are serial TDM data inputs from the |
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| three codecs. The serial input is |
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| rate of 24 Mb/s for Intel High Definition Audio. |
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NOTE Some signals have special functionality during the reset process. They may bootstrap some basic important functions of the module.
26 | Reference Manual | COM 830 |
