Chapter 3Signals and Pinout Tables

Table 3-20. SDVO Signal Descriptions

Signal

Description

I/O

PU/PD

Comment

SDVOB_RED+

Serial Digital Video B red output

O PCIE

 

 

SDVOB_RED-

differential pair Multiplexed with

 

 

 

 

PEG_TX[0]+ and PEG_TX[0]- pair

 

 

 

SDVOB_GRN+

Serial Digital Video B green output

O PCIE

 

 

SDVOB_GRN-

differential pair Multiplexed with

 

 

 

 

PEG_TX[1]+ and PEG_TX[1]-

 

 

 

SDVOB_BLU+

Serial Digital Video B blue output

O PCIE

 

 

SDVOB_BLU-

differential pair Multiplexed with

 

 

 

 

PEG_TX[2]+ and PEG_TX[2]-

 

 

 

SDVOB_CK+

Serial Digital Video B clock output

O PCIE

 

 

SDVOB_CK-

differential pair. Multiplexed with

 

 

 

 

PEG_TX[3]+ and PEG_TX[3]-

 

 

 

SDVOB_INT+

Serial Digital Video B interrupt input

I PCIE

 

 

SDVOB_INT-

differential pair. Multiplexed with

 

 

 

 

PEG_RX[1]+ and PEG_RX[1]-

 

 

 

SDVOC_RED+

Serial Digital Video C red output

O PCIE

 

 

SDVOC_RED-

differential pair. Multiplexed with

 

 

 

 

PEG_TX[4]+ and PEG_TX[4]-

 

 

 

SDVOC_GRN+

Serial Digital Video C green output

O PCIE

 

 

SDVOC_GRN-

differential pair. Multiplexed with

 

 

 

 

PEG_TX[5]+ and PEG_TX[5]-

 

 

 

SDVOC_BLU+

Serial Digital Video C blue output

O PCIE

 

 

SDVOC_BLU-

differential pair. Multiplexed with

 

 

 

 

PEG_TX[6]+ and PEG_TX[6]-

 

 

 

SDVOC_CK+

Serial Digital Video C clock output

O PCIE

 

 

SDVOC_CK-

differential pair. Multiplexed with

 

 

 

 

PEG_TX[7]+ and PEG_TX[7]-

 

 

 

SDVOC_INT+

Serial Digital Video C interrupt input

I PCIE

 

 

SDVOC_INT-

differential pair. Multiplexed with

 

 

 

 

PEG_RX[5]+ and PEG_RX[5]-

 

 

 

SDVO_TVCLKIN+

Serial Digital Video TVOUT

I PCIE

 

 

SDVO_TVCLKIN-

synchronization clock input

 

 

 

 

differential pair. Multiplexed with

 

 

 

 

PEG_RX[0]+ and PEG_RX[0]-

 

 

 

SDVO_FLDSTALL+

Serial Digital Video Field Stall input

I PCIE

 

 

SDVO_FLDSTALL-

differential pair. Multiplexed with

 

 

 

 

PEG_RX[2]+ and PEG_RX[2]-

 

 

 

SDVO_I2C_CK

SDVO I²C clock line to set up SDVO

O 2.5V

 

 

(SDVO_CLK)

peripherals.

 

 

 

 

 

 

 

 

 

 

 

 

SDVO_I2C_DAT

SDVO I²C data line to set up SDVO

I/O OD

 

SDVO_I2C_

(SDVO_DATA)

peripherals.

2.5V

 

DAT is a

 

 

 

boot strap

 

 

 

 

 

 

 

 

signal (see

 

 

 

 

note below)

 

 

 

 

 

COM 830

Reference Manual

41

Page 46 Page 48
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Image 47
Ampro Corporation COM 830 Sdvobred+, Pcie Sdvobred, Sdvobgrn+, Pcie Sdvobgrn, Sdvobblu+, Pcie Sdvobblu, Sdvobck+, Sdvocck+
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