32 Datasheet
Electrical Specifications
2.7 Clock Specifications2.7.1 FSB Clock (BCLK[1:0]) and Processor Clocking
BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the processor.
As in previous generation processors, the Pentium D processor core frequency is a multiple of the
BCLK[1:0] frequency. The processor bus ratio multiplier will be set at its default ratio during
manufacturing. The Pentium D processor uses a differential clocking implementation.
2.7.2 FSB Frequency Select Signals
Upon power up, the front side bus frequency is set to the maximum supported by the individual
processor. BSEL[2:0] are open-drain outputs that must be pulled up to VTT, and are used to select
the front side bus frequency. Refer to Table 2- 10 for DC specifications. Table 2-18 defines the
possible combinations of the signals and the frequency associated with each combination. The
frequency is determined by the processor(s), chipset, and clock synthesizer. Individual processors
will only operate at their specified front side bus clock frequency.
The Pentium D processor 840, 830, and 820 operate at 800 MHz FSB frequency (selected by a
200 MHz BCLK[1:0] frequency). The Pentium processor 805 operates at 533 MHz FSB frequency
(selected by a 133 MHz BCLK[1:0] frequency).
Table 2-17. Core Frequency to FSB Multiplier Configuration
Multiplication of System Core
Frequency to FSB Frequency
Core Frequency
(133MHz BCLK/
533MHz FSB)
Core Frequency
(200MHz BCLK/
800MHz FSB) Notes1, 2
NOTES:
1. Individual processors operate only at or below the rated frequency.
2. Listed frequencies are not necessarily committed production frequencies.
1/14 RESERVED 2.80 GHz -
1/15 RESERVED 3 GHz -
1/16 RESERVED 3.20 GHz -
1/17 RESERVED RESERVED -
1/18 RESERVED RESERVED -
1/19 RESERVED RESERVED -
1/20 2.66GHz RESERVED -
1/21 RESERVED RESERVED -