Electrical Specifications

Table 2-7. FSB Signal Groups

Signal Group

Type

Signals1

GTL+ Common Clock

Synchronous to BCLK[1:0]

BPRI#, DEFER#, RESET#, RS[2:0]#, RSP#, TRDY#,

Input

 

 

 

 

 

 

 

AP[1:0]#, ADS#, BINIT#, BNR#, BPM[5:0]#, BR0#,

GTL+ Common Clock I/O

Synchronous to BCLK[1:0]

DBSY#, DP[3:0]#, DRDY#, HIT#, HITM#, LOCK#,

 

 

MCERR#

 

 

Signals

Associated Strobe

 

 

REQ[4:0]#, A[16:3]#

ADSTB0#

GTL+ Source

Synchronous to assoc.

A[35:17]#

ADSTB1#

Synchronous I/O

strobe2

D[15:0]#, DBI0#

DSTBP0#, DSTBN0#

 

 

D[31:16]#, DBI1#

DSTBP1#, DSTBN1#

 

 

D[47:32]#, DBI2#

DSTBP2#, DSTBN2#

 

 

D[63:48]#, DBI3#

DSTBP3#, DSTBN3#

 

 

 

GTL+ Strobes

Synchronous to BCLK[1:0]

ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#

 

 

 

GTL+ Asynchronous

 

A20M#, FORCEPR#, IGNNE#, INIT#, LINT0/INTR,

Input

 

LINT1/NMI, SMI#, STPCLK#

 

 

 

 

GTL+ Asynchronous

 

FERR#/PBE#, IERR#, THERMTRIP#

Output

 

 

 

 

 

 

 

 

GTL+ Asynchronous

 

PROCHOT#

 

Input/Output

 

 

 

 

 

 

 

 

 

TAP Input

Synchronous to TCK

TCK, TDI, TMS, TRST#

 

 

 

 

 

TAP Output

Synchronous to TCK

TDO

 

 

 

 

 

FSB Clock

Clock

BCLK[1:0], ITP_CLK[1:0]3

 

 

 

VCC, VTT, VCCA, VCCIOPLL, VID[5:0], VSS, VSSA,

 

 

GTLREF[1:0], COMP[1:0], COMP[3:2], IMPSEL,

 

 

RESERVED, TESTHI[13:0], THERMDA, THERMDC,

Power/Other

 

VCC_SENSE, VSS_SENSE, BSEL[2:0], SKTOCC#,

 

DBR#3, VTTPWRGD, BOOTSELECT, PWRGOOD,

 

 

VTT_OUT_LEFT, VTT_OUT_RIGHT, VTT_SEL,

 

 

LL_ID[1:0], FCx, VCC_MB_REGULATION,

 

 

VSS_MB_REGULATION, MSID[1:0], VCCPLL

 

 

 

 

NOTES:

 

 

 

1.Refer to Section 4.2 for signal descriptions.

2.The value of A[16:3]# and A[35:17]# during the active-to-inactive edge of RESET# defines the processor configuration options. See Section 6.1 for details.

3.In processor systems where there is no debug port implemented on the system board, these signals are used to support a debug port interposer. In systems with the debug port implemented on the system board, these signals are no connects.

Table 2-8outlines the signals which include on-die termination (RTT). Open drain signals are also included. Table 2-9provides signal reference voltages.

Datasheet

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Image 27
Intel 830 manual FSB Signal Groups, Signals Associated Strobe

830 specifications

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