72 Datasheet
Land Listing and Signal Descriptions
RSP# Input
RSP# (Response Parity) is driven by the response agent (the agent responsible
for completion of the current transaction) during assertion of RS[2:0]#, the
signals for which RSP# provides parity protection. It must connect to the
appropriate pins/lands of all processor FSB agents.
A correct parity signal is high if an even number of covered signals are low and
low if an odd number of covered signals are low. While RS[2:0]# = 000, RSP# is
also high, since this indicates it is not being driven by any agent ensuring
correct parity.
SKTOCC# Output SKTOCC# (Socket Occupied) will be pulled to ground by the processor. System
board designers may use this signal to determine if the processor is present.
SMI# Input
SMI# (System Management Interrupt) is asserted asynchronously by system
logic. On accepting a System Management Interrupt, the processor saves the
current state and enters System Management Mode (SMM). An SMI
Acknowledge transaction is issued, and the processor begins program
execution from the SMM handler.
If SMI# is asserted during the de-assertion of RESET#, the processor will tri-
state its outputs.
STPCLK# Input
STPCLK# (Stop Clock), when asserted, causes the processor to enter a low
power Stop-Grant state. The processor issues a Stop-Grant Acknowledge
transaction, and stops providing internal clock signals to all processor core units
except the FSB and APIC units. The processor continues to snoop bus
transactions and service interrupts while in Stop-Grant state. When STPCLK# is
de-asserted, the processor restarts its internal clock to all units and resumes
execution. The assertion of STPCLK# has no effect on the bus clock; STPCLK#
is an asynchronous input.
TCK Input TCK (Test Clock) provides the clock input for the processor Test Bus (also
known as the Test Access Port).
TDI Input TDI (Test Data In) transfers serial test data into the processor. TDI provides the
serial input needed for JTAG specification support.
TDO Output TDO (Test Data Out) transfers serial test data out of the processor. TDO
provides the serial output needed for JTAG specification support.
TESTHI[13:0] Input TESTHI[13:0] must be connected to the processor’s appropriate power source
(refer to VTT_OUT_LEFT and VTT_OUT_RIGHT signal description) through a
resistor for proper processor operation. See Section 2.4 for more details.
THERMDA Other Thermal Diode Anode. See Section5.2.7.
THERMDC Other Thermal Diode Cathode. See Section5.2.7.
THERMTRIP# Output
In the event of a catastrophic cooling failure, the processor will automatically
shut down when the silicon has reached a temperature approximately 20 °C
above the maximum TC. Assertion of THERMTRIP# (Thermal Trip) indicates the
processor junction temperature has reached a level beyond where permanent
silicon damage may occur. Upon assertion of THERMTRIP#, the processor will
shut off its internal clocks (thus, halting program execution) in an attempt to
reduce the processor junction temperature. To protect the processor, its core
voltage (VCC) must be removed following the assertion of THERMTRIP#.
Driving of the THERMTRIP# signal is enabled within 10 us of the assertion of
PWRGOOD (provided VTTPWRGD, VTT, and VCC are asserted) and is
disabled on de-assertion of PWRGOOD (if VTTPWRGD, VTT, or VCC are not
valid, THERMTRIP# may also be disabled). Once activated, THERMTRIP#
remains latched until PWRGOOD, VTTPWRGD, VTT or VCC is de-asserted.
While the de-assertion of the PWRGOOD, VTTPWRGD, VTT or VCC signal will
de-assert THERMTRIP#, if the processor’s junction temperature remains at or
above the trip level, THERMTRIP# will again be asserted within 10 us of the
assertion of PWRGOOD (provided VTTPWRGD, VTT, and VCC are
asserted).THERMTRIP# should not be sampled until 10 us after PWRGOOD
assertion.
Table 4-3. Signal Description (Sheet 7 of 8)
Name Type Description