Intel 830 6.2.3 Stop-Grant State

Datasheet 87

Features

The system can generate a STPCLK# while the processor is in the HALT Power Down state. When

the system deasserts the STPCLK# interrupt, the processor will return execution to the HALT state.

While in HALT Power Down state, the processor will process bus snoops.

Enhanced HALT is a low power state entered when all logical processors have executed the HALT

or MWAIT instructions and Enhanced HALT has been enabled via the BIOS. When one of the

logical processors executes the HALT instruction, that logical processor is halted; however, the

other processor continues normal operation.

The processor will automatically transition to a lower frequency and voltage operating point before

entering the Enhanced HALT state. Note that the processor FSB frequency is not altered; only the

internal core frequency is changed. When entering the low power state, the processor will first

switch to the lower bus ratio and then transition to the lower VID.

While in Enhanced HALT state, the processor will process bus snoops.

The processor exits the Enhanced HALT state when a break event occurs. When the processor exits

the Enhanced HALT state, it will first transition the VID to the original value and then change the

bus ratio back to the original value.

6.2.3 Stop-Grant State

When the STPCLK# signal is asserted, the Stop-Grant state of the processor is entered 20 bus

clocks after the response phase of the processor-issued Stop Grant Acknowledge special bus cycle.

Since the GTL+ signals receive power from the FSB, these signals should not be driven (allowing

the level to return to VTT) for minimum power drawn by the termination resistors in this state. In

addition, all other input signals on the FSB should be driven to the inactive state.

BINIT# will not be serviced while the processor is in Stop-Grant state. The event will be latched

and can be serviced by software upon exit from the Stop Grant state.

RESET# will cause the processor to immediately initialize itself, but the processor will stay in

Stop-Grant state. A transition back to the Normal state will occur with the de-assertion of the

STPCLK# signal.

A transition to the HALT/Grant Snoop state will occur when the processor detects a snoop on the

FSB (see Section6.2.4).

While in the Stop-Grant State, SMI#, INIT#, BINIT# and LINT[1:0] will be latched by the

processor, and only serviced when the processor returns to the Normal State. Only one occurrence

of each event will be recognized upon return to the Normal state.

While in Stop-Grant state, the processor will process a FSB snoop.