Intel 830 Table 2-3. Voltage and Current Specifications

20 Datasheet

Electrical Specifications

Table 2-3. Voltage and Current Specifications

Symbol Parameter Min Typ Max Unit Notes

VID range VID 1.200 — 1.400 V 1

NOTES:

1. Individual processor VID values may be calibrated during manufacturing such that two devices at the same speed may have different VID settings.

Processor number Core Frequency

VCC

840

830

VCC for 775_VR_CONFIG_05B

processor (PRB = 1)

3.20GHz

3GHz

Refer to Table2-5 and

Figure2-2 V2, 3, 4, 5

2. These voltages are targets only. A variable voltage source should exist on systems in the event that a different voltage is required. See Section2.3

and Table2-1 for more information.

3. The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE lands at the socket with a 100 MHz bandwidth oscillo-

scope, 1.5 pF maximum probe capacitance, and 1 MΩ minimum impedance. The maximum length of ground wire on the probe should be less than

5 mm. Ensure external noise from the system is not coupled into the oscilloscope probe.

4. Refer to Table2-5 and Figure 2-2 for the minimum, typical, and maximum VCC allowed for a given current. The processor should not be subjected

to any VCC and ICC combination wherein VCC exceeds VCC_MAX for a given current.

820

805

VCC for 775_VR_CONFIG_05A

processor (PRB = 0)

2.80GHz

2.66GHz

Refer to Table2-4 and

Figure2-1 V2, 3, 5, 6, 7

ICC

840

830

ICC for 775_VR_CONFIG_05B Pentium

D processor (PRB = 1)

3.20GHz

3GHz

——

125

125 A 8

820

805

ICC for 775_VR_CONFIG_05A Pentium

D processor (PRB = 0)

2.80 GHz

2.66GHz

——

100

100

ICC_RESET

840

830

820

805

ICC when PWRGOOD and RESET# are

active

3.20GHz

3GHz

2.80GHz

2.66GHz

——

125

125

106

106

A9

ISGNT 840/830/820/805

ICC Stop-Grant

3.20/3/2.80/2.66GHz ——65 A 10, 11, 12

IENHANCED_HALT 840/830/820/805

ICC Enhanced Halt

3.20/3/2.80/2.66GHz ——50 A 11, 12

ITCC ICC TCC active — — ICC A13

VTT VTT for 775_VTT_CONFIG_2 processors:

FSB termination voltage (DC+AC specifications) 1.14 1.20 1.26 V14, 15

VTT_OUT ICC DC Current that may be drawn from VTT_OUT per pin — — 580 mA -

ITT FSB termination current — — 4.7 A 12, 16

ICC_VCCA ICC for PLL lands — — 120 mA 12

ICC_VCCIOPLL ICC for I/O PLL land — — 100 mA 12

ICC_GTLREF ICC for GTLREF — — 200 μA12

Contents

Main Contents Contents Page Figures Tables Revision History Page Intel Pentium D Processor 800 Sequence Features Page 1 1.1 Terminology 1.1.1 Processor Packaging Terminology Introduction 1.2 References Table 1-1. References Page 2 2.1 Power and Ground Lands 2.2 Decoupling Guidelines 2.2.1 VCC Decoupling 2.2.2 VTT Decoupling 2.3 Voltage Identification Table 2-1. Voltage Identification Definition 2.4 Reserved, Unused, FC and TESTHI Signals 2.5 Voltage and Current Specifications 2.5.1 Absolute Maximum and Minimum Ratings 2.5.2 DC Voltage and Current Specifications Table 2-3. Voltage and Current Specifications Table 2-4. VCC Static and Transient Tolerance for 775_VR_CONFIG_05A Pentium D Processor Figure 2-1. VCC Static and Transient Tolerance for 775_VR_CONFIG_05A Pentium D Processor Table 2-5. VCC Static and Transient Tolerance for 775_VR_CONFIG_05B Pentium D Processor Figure 2-2. VCC Static and Transient Tolerance for 775_VR_CONFIG_05B Pentium D Processor 2.5.3 VCC Overshoot Specification Time Example Overshoot Waveform T VID 2.6 Signaling Specifications 2.6.1 FSB Signal Groups Table 2-7. FSB Signal Groups 2.6.2 GTL+ Asynchronous Signals Table 2-8. Signal Characteristics Table 2-9. Signal Reference Voltages 2.6.3 FSB DC Specifications Table 2-11. GTL+ Signal Group DC Specifications Table 2-12. PWRGOOD Input and TAP Signal Group DC Specifications Table 2-13. GTL+ Asynchronous Signal Group DC Specifications 2.6.3.1 GTL+ Front Side Bus Specifications Table 2-14. VTTPWRGD DC Specifications Table 2-15. BOOTSELECT and MSID[1:0] DC Specifications Table 2-16. GTL+ Bus Voltage Definitions 2.7 Clock Specifications 2.7.1 FSB Clock (BCLK[1:0]) and Processor Clocking 2.7.2 FSB Frequency Select Signals 2.7.3 Phase Lock Loop (PLL) and Filter Figure 2-4. Phase Lock Loop (PLL) Filter Requirements 3 Specifications 3.1 Package Mechanical Drawing Page Page Page 3.2 Processor Component Keep-Out Zones 3.3 Package Loading Specifications 3.4 Package Handling Guidelines 3.5 Package Insertion Specifications 3.6 Processor Mass Specification 3.7 Processor Materials 3.8 Processor Markings Page Package Mechanical Specifications 3.9 Processor Land Coordinates Figure 3-7. Processor Land Coordinates, Top View Socket LGA775 Quadrants Top View V CC / V VTT / Clocks Data 4 Figure 4-1. Landout Diagram (Top View Left Side) Figure 4-2. Landout Diagram (Top View Right Side) Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page 4.2 Alphabetical Signals Reference Table 4-3. Signal Description (Sheet 1 of 8) Table 4-3. Signal Description (Sheet 2 of 8) Table 4-3. Signal Description (Sheet 3 of 8) Table 4-3. Signal Description (Sheet 4 of 8) Table 4-3. Signal Description (Sheet 5 of 8) Table 4-3. Signal Description (Sheet 6 of 8) Table 4-3. Signal Description (Sheet 7 of 8) Table 4-3. Signal Description (Sheet 8 of 8) Page 5 Design Considerations 5.1 Processor Thermal Specifications 5.1.1 Thermal Specifications Page Figure 5-1. Thermal Profile for the Pentium D Processor with PRB=1 Figure 5-2. Thermal Profile for the Pentium D Processor with PRB=0 5.1.2 Thermal Metrology 5.2 Processor Thermal Features 5.2.1 Thermal Monitor 5.2.2 On-Demand Mode 5.2.3 PROCHOT# Signal 5.2.4 FORCEPR# Signal Pin 5.2.5 THERMTRIP# Signal 5.2.6 TCONTROL and Fan Speed Reduction 5.2.7 Thermal Diode Page Page 6 6.1 Power-On Configuration Options 6.2 Clock Control and Low Power States 6.2.1 Normal State 6.2.2 HALT and Enhanced HALT Powerdown States 6.2.2.1 HALT Powerdown State 6.2.2.2 Enhanced HALT Powerdown State 6.2.3 Stop-Grant State 6.2.4 Enhanced HALT Snoop or HALT Snoop State, Grant Snoop State 6.2.4.1 HALT Snoop State, Grant Snoop State 6.2.4.2 Enhanced HALT Snoop State 6.2.5 Enhanced Intel SpeedStep Techn olo gy 7 7.1 Mechanical Specifications 7.1.1 Boxed Processor Cooling Solution Dimensions 7.1.2 Boxed Processor Fan Heatsink Weight 7.1.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly 7.2 Electrical Requirements 7.2.1 Fan Heatsink Power Supply Page 7.3 Thermal Specifications 7.3.1 Boxed Processor Cooling Requirements Page 7.3.2 Variable Speed Fan Page 8 (BTX) Type I Boxed Processor Specifications 8.1 Mechanical Specifications 8.1.1 Cooling Solution Dimensions 8.1.2 Boxed Processor Fan Heatsink Weight 8.1.3 Boxed Processor Support and Retention Module (SRM) 8.2 Electrical Requirements 8.2.1 Fan Heatsink Power Supply Page 8.3 Thermal Specifications 8.3.1 Boxed Processor Cooling Requirements 8.3.2 Variable Speed Fan Page Page 9 9.1 Logic Analyzer Interface (LAI) 9.1.1 Mechanical Considerations 9.1.2 Electrical Considerations