Intel 830 manual Signal Description Sheet 8

			Land Listing and Signal Descriptions
Table 4-3. Signal Description (Sheet 8 of 8)
	Name	Type	Description
	TMS	Input	TMS (Test Mode Select) is a JTAG specification support signal used by debug
			tools.
			TRDY# (Target Ready) is asserted by the target to indicate that it is ready to
	TRDY#	Input	receive a write or implicit writeback data transfer. TRDY# must connect the
			appropriate pins/lands of all FSB agents.
			TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be
	TRST#	Input	driven low during power on Reset. Refer to the eXtended Debug Port: Debug
			Port Design Guide for UP and DP Platforms for complete implementation
			details.
	VCC	Input	VCC are the power pins for the processor. The voltage supplied to these pins is
			determined by the VID[5:0] pins.
	VCCA	Input	VCCA provides isolated power for the internal processor core PLLs.
	VCCIOPLL	Input	VCCIOPLL provides isolated power for internal processor FSB PLLs.
	VCCPLL	Input	VCCPLL is available for compatibility with future processors.
			VCC_SENSE is an isolated low impedance connection to processor core power
	VCC_SENSE	Output	(VCC). It can be used to sense or measure voltage near the silicon with little
			noise.
	VCC_MB_		This land is provided as a voltage regulator feedback sense point for VCC. It is
		Output	connected internally in the processor package to the sense point land U27 as
	REGULATION		described in the Voltage Regulator-Down (VRD) 10.1 Design Guide for Desktop
			Socket 775.
			VID[5:0] (Voltage ID) signals are used to support automatic selection of power
			supply voltages (VCC). These are open drain signals that are driven by the
			processor and must be pulled up on the motherboard. Refer to the Voltage
			Regulator-Down (VRD) 10.1 Design Guide for Desktop Socket 775 for more
	VID[5:0]	Output	information.
			The voltage supply for these signals must be valid before the VR can supply
			VCC to the processor. Conversely, the VR output must be disabled until the
			voltage supply for the VID signals becomes valid. The VID signals are needed
			to support the processor voltage specification variations. See Table 2-1for
			definitions of these signals. The VR must supply the voltage that is requested
			by the signals, or disable itself.
	VSS	Input	VSS are the ground lands for the processor and should be connected to the
			system ground plane.
	VSSA	Input	VSSA is the isolated ground for internal PLLs.
	VSS_SENSE	Output	VSS_SENSE is an isolated low impedance connection to processor core VSS. It
			can be used to sense or measure ground near the silicon with little noise.
	VSS_MB_		This land is provided as a voltage regulator feedback sense point for VSS. It is
		Output	connected internally in the processor package to the sense point land V27 as
	REGULATION		described in the Voltage Regulator-Down (VRD) 10.1 Design Guide for Desktop
			Socket 775.
	VTT		Miscellaneous voltage supply.
	VTT_OUT_LEFT		The VTT_OUT_LEFT and VTT_OUT_RIGHT signals are included to provide a
		Output	voltage supply for some signals that require termination to VTT on the
	VTT_OUT_RIGHT
			motherboard.
	VTT_SEL	Output	The VTT_SEL signal is used to select the correct VTT voltage level for the
			processor.
	VTTPWRGD	Input	The processor requires this input to determine that the VTT voltages are stable
			and within specification.
			§

Datasheet 73