Datasheet 71
Land Listing and Signal Descriptions
MCERR# Input/
Output
MCERR# (Machine Check Error) is asserted to indicate an unrecoverable error
without a bus protocol violation. It may be driven by all processor FSB agents.
MCERR# assertion conditions are configurable at a system level. Assertion
options are defined by the following options:
• Enabled or disabled.
• Asserted, if configured, for internal errors along with IERR#.
• Asserted, if configured, by the request initiator of a bus transaction after it
observes an error.
• Asserted by any bus agent when it observes an error in a bus transaction.
For more details regarding machine check architecture, refer to the IA-32
Software Developer’s Manual, Volume 3: System Programming Guide.
MSID[1:0] Input
MSID0 is used to indicate to the processor whether the platform supports
processors with the Platform Requirement Bit (PRB) set. A processor with
PRB = 1 will only boot if its MSID0 pin is electrically low. A processor with
PRB = 0 will ignore this input.
MSID1 is ignored by the processor.
PROCHOT#
Output
or
Input/
Output
For the Pentium D processor PROCHOT# can be configured via BIOS as an
output or a bi-directional signal.
As an output, PROCHOT# (Processor Hot) will go active when the processor
temperature monitoring sensor detects that one or both cores has reached its
maximum safe operating temperature. This indicates that the processor
Thermal Control Circuit (TCC) has been activated, if enabled.
As a bi-directional signal, assertion of PROCHOT# by the system will activate
the TCC, if enabled, for both cores. The TCC will remain active until the system
de-asserts PROCHOT#. See Section5.2.3 for more details.
PWRGOOD Input
PWRGOOD (Power Good) is a processor input. The processor requires this
signal to be a clean indication that the clocks and power supplies are stable and
within their specifications. ‘Clean’ implies that the signal will remain low
(capable of sinking leakage current), without glitches, from the time that the
power supplies are turned on until they come within specification. The signal
must then transition monotonically to a high state. PWRGOOD can be driven
inactive at any time, but clocks and power must again be stable before a
subsequent rising edge of PWRGOOD.
The PWRGOOD signal must be supplied to the processor; it is used to protect
internal circuits against voltage sequencing issues. It should be driven high
throughout boundary scan operation.
REQ[4:0]# Input/
Output
REQ[4:0]# (Request Command) must connect the appropriate pins/lands of all
processor FSB agents. They are asserted by the current bus owner to define
the currently active transaction type. These signals are source synchronous to
ADSTB0#. Refer to the AP[1:0]# signal description for a details on parity
checking of these signals.
RESET# Input
Asserting the RESET# signal resets the processor to a known state and
invalidates its internal caches without writing back any of their contents. For a
power-on Reset, RESET# must stay active for at least one millisecond after
VCC and BCLK have reached their proper specifications. On observing active
RESET#, all FSB agents will de-assert their outputs within two clocks. RESET#
must not be kept asserted for more than 10ms while PWRGOOD is asserted.
A number of bus signals are sampled at the active-to-inactive transition of
RESET# for power-on configuration. These configuration options are described
in the Section6.1.
This signal does not have on-die termination and must be terminated on the
system board.
RS[2:0]# Input RS[2:0]# (Response Status) are driven by the response agent (the agent
responsible for completion of the current transaction), and must connect the
appropriate pins/lands of all processor FSB agents.
Table 4-3. Signal Description (Sheet 6 of 8)Name Type Description