Electrical Specifications

Table 2-8. Signal Characteristics

Signals with RTT

Signals with no RTT

 

 

A[35:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#, BINIT#,

A20M#, BCLK[1:0], BPM[5:0]#, BR0#, BSEL[2:0],

BNR#, BOOTSELECT1, BPRI#, D[63:0]#,

DBI[3:0]#, DBSY#, DEFER#, DP[3:0]#, DRDY#,

COMP[3:0], FERR#/PBE#, IERR#, IGNNE#, INIT#,

LINT0/INTR, LINT1/NMI, PWRGOOD, RESET#,

DSTBN[3:0]#, DSTBP[3:0]#, FORCEPR#, HIT#,

SKTOCC#, SMI#, STPCLK#, TDO, TESTHI[13:0],

HITM#, IMPSEL1, LOCK#, MCERR#,

PROCHOT#, REQ[4:0]#, RS[2:0]#, RSP#,

THERMDA, THERMDC, THERMTRIP#, VID[5:0],

VTTPWRGD, GTLREF[1:0], TCK, TDI, TRST#, TMS

TRDY#, MSID[1:0]1

Open Drain Signals2

 

BSEL[2:0], VID[5:0], THERMTRIP#, FERR#/

 

PBE#, IERR#, BPM[5:0]#, BR0#, TDO, VTT_SEL,

 

LL_ID[1:0]

 

 

 

NOTES:

 

1.These signals have a 250–5000 Ω pullup to VTT rather than on-die termination.

2.Signals that do not have RTT, nor are actively driven to their high-voltage level.

Table 2-9. Signal Reference Voltages

GTLREF

VTT/2

BPM[5:0]#, LINT0/INTR, LINT1/NMI, RESET#,

 

BINIT#, BNR#, HIT#, HITM#, MCERR#, PROCHOT#,

BOOTSELECT, VTTPWRGD, A20M#, IGNNE#,

BR0#, A[35:0]#, ADS#, ADSTB[1:0]#, AP[1:0]#,

INIT#, PWRGOOD1, SMI#, STPCLK#, TCK1, TDI1,

BPRI#, D[63:0]#, DBI[3:0]#, DBSY#, DEFER#,

TMS1, TRST#1, MSID[1:0]

DP[3:0]#, DRDY#, DSTBN[3:0]#, DSTBP[3:0]#,

 

LOCK#, REQ[4:0]#, RS[2:0]#, RSP#, TRDY#

 

 

 

NOTES:

1. These signals also have hysteresis added to the reference voltage. See Table 2-12for more information.

2.6.2GTL+ Asynchronous Signals

The signals A20M#, IGNNE#, INIT#, SMI#, and STPCLK# utilize CMOS input buffers. GTL+ asynchronous signals follow the same DC requirements as GTL+ signals; however, the outputs are not actively driven high (during a logical 0 to 1 transition) by the processor. GTL+ asynchronous signals do not have setup or hold time specifications in relation to BCLK[1:0].

All of the GTL+ Asynchronous signals are required to be asserted/deasserted for at least six BCLKs in order for the processor to recognize the proper signal state. See Section 2.6.3 for the DC specifications for the GTL+ Asynchronous signal groups. See Table 6.2 for additional timing requirements for entering and leaving the low power states.

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Datasheet

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Intel 830 manual 2 GTL+ Asynchronous Signals, Signal Characteristics, Signal Reference Voltages

830 specifications

The Intel 830 chipset, introduced in the early 2000s, marked a significant evolution in Intel's chipset architecture for desktop and mobile computing. Known for its support of the Pentium 4 processors, the 830 chipset was tailored for both performance and stability, making it an appealing choice for OEMs and enthusiasts alike.

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