Intel 830 2.6.2 GTL+ Asynchronous Signals

28 Datasheet

Electrical Specifications

2.6.2 GTL+ Asynchronous Signals

The signals A20M#, IGNNE#, INIT#, SMI#, and STPCLK# utilize CMOS input buffers. GTL+

asynchronous signals follow the same DC requirements as GTL+ signals; however, the outputs are

not actively driven high (during a logical 0 to 1 transition) by the processor. GTL+ asynchronous

signals do not have setup or hold time specifications in relation to BCLK[1:0].

All of the GTL+ Asynchronous signals are required to be asserted/deasserted for at least six

BCLKs in order for the processor to recognize the proper signal state. See Section 2.6.3 for the DC

specifications for the GTL+ Asynchronous signal groups. See Table 6. 2 for additional timing

requirements for entering and leaving the low power states.

Table 2-8. Signal Characteristics

Signals with RTT Signals with no RTT

A[35:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#, BINIT#,

BNR#, BOOTSELECT1, BPRI#, D[63:0]#,

DBI[3:0]#, DBSY#, DEFER#, DP[3:0]#, DRDY#,

DSTBN[3:0]#, DSTBP[3:0]#, FORCEPR#, HIT#,

HITM#, IMPSEL1, LOCK#, MCERR#,

PROCHOT#, REQ[4:0]#, RS[2:0]#, RSP#,

TRDY#, MSID[1:0]1

NOTES:

1. These signals have a 250–5000 Ω pullup to VTT rather than on-die termination.

A20M#, BCLK[1:0], BPM[5:0]#, BR0#, BSEL[2:0],

COMP[3:0], FERR#/PBE#, IERR#, IGNNE#, INIT#,

LINT0/INTR, LINT1/NMI, PWRGOOD, RESET#,

SKTOCC#, SMI#, STPCLK#, TDO, TESTHI[13:0],

THERMDA, THERMDC, THERMTRIP#, VID[5:0],

VTTPWRGD, GTLREF[1:0], TCK, TDI, TRST#, TMS

Open Drain Signals2

2. Signals that do not have RTT, nor are actively driven to their high-voltage level.

BSEL[2:0], VID[5:0], THERMTRIP#, FERR#/

PBE#, IERR#, BPM[5:0]#, BR0#, TDO, VTT_SEL,

LL_ID[1:0]

Table 2-9. Signal Reference Voltages

GTLREF V TT/2

BPM[5:0]#, LINT0/INTR, LINT1/NMI, RESET#,

BINIT#, BNR#, HIT#, HITM#, MCERR#, PROCHOT#,

BR0#, A[35:0]#, ADS#, ADSTB[1:0]#, AP[1:0]#,

BPRI#, D[63:0]#, DBI[3:0]#, DBSY#, DEFER#,

DP[3:0]#, DRDY#, DSTBN[3:0]#, DSTBP[3:0]#,

LOCK#, REQ[4:0]#, RS[2:0]#, RSP#, TRDY#

BOOTSELECT, VTTPWRGD, A20M#, IGNNE#,

INIT#, PWRGOOD1, SMI#, STPCLK#, TCK1, TDI1,

TMS1, TRST#1, MSID[1:0]

NOTES:

1. These signals also have hysteresis added to the reference voltage. See Table2-12 for more information.

Contents

Main Contents Contents Page Figures Tables Revision History Page Intel Pentium D Processor 800 Sequence Features Page 1 1.1 Terminology 1.1.1 Processor Packaging Terminology Introduction 1.2 References Table 1-1. References Page 2 2.1 Power and Ground Lands 2.2 Decoupling Guidelines 2.2.1 VCC Decoupling 2.2.2 VTT Decoupling 2.3 Voltage Identification Table 2-1. Voltage Identification Definition 2.4 Reserved, Unused, FC and TESTHI Signals 2.5 Voltage and Current Specifications 2.5.1 Absolute Maximum and Minimum Ratings 2.5.2 DC Voltage and Current Specifications Table 2-3. Voltage and Current Specifications Table 2-4. VCC Static and Transient Tolerance for 775_VR_CONFIG_05A Pentium D Processor Figure 2-1. VCC Static and Transient Tolerance for 775_VR_CONFIG_05A Pentium D Processor Table 2-5. VCC Static and Transient Tolerance for 775_VR_CONFIG_05B Pentium D Processor Figure 2-2. VCC Static and Transient Tolerance for 775_VR_CONFIG_05B Pentium D Processor 2.5.3 VCC Overshoot Specification Time Example Overshoot Waveform T VID 2.6 Signaling Specifications 2.6.1 FSB Signal Groups Table 2-7. FSB Signal Groups 2.6.2 GTL+ Asynchronous Signals Table 2-8. Signal Characteristics Table 2-9. Signal Reference Voltages 2.6.3 FSB DC Specifications Table 2-11. GTL+ Signal Group DC Specifications Table 2-12. PWRGOOD Input and TAP Signal Group DC Specifications Table 2-13. GTL+ Asynchronous Signal Group DC Specifications 2.6.3.1 GTL+ Front Side Bus Specifications Table 2-14. VTTPWRGD DC Specifications Table 2-15. BOOTSELECT and MSID[1:0] DC Specifications Table 2-16. GTL+ Bus Voltage Definitions 2.7 Clock Specifications 2.7.1 FSB Clock (BCLK[1:0]) and Processor Clocking 2.7.2 FSB Frequency Select Signals 2.7.3 Phase Lock Loop (PLL) and Filter Figure 2-4. Phase Lock Loop (PLL) Filter Requirements 3 Specifications 3.1 Package Mechanical Drawing Page Page Page 3.2 Processor Component Keep-Out Zones 3.3 Package Loading Specifications 3.4 Package Handling Guidelines 3.5 Package Insertion Specifications 3.6 Processor Mass Specification 3.7 Processor Materials 3.8 Processor Markings Page Package Mechanical Specifications 3.9 Processor Land Coordinates Figure 3-7. Processor Land Coordinates, Top View Socket LGA775 Quadrants Top View V CC / V VTT / Clocks Data 4 Figure 4-1. Landout Diagram (Top View Left Side) Figure 4-2. Landout Diagram (Top View Right Side) Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page 4.2 Alphabetical Signals Reference Table 4-3. Signal Description (Sheet 1 of 8) Table 4-3. Signal Description (Sheet 2 of 8) Table 4-3. Signal Description (Sheet 3 of 8) Table 4-3. Signal Description (Sheet 4 of 8) Table 4-3. Signal Description (Sheet 5 of 8) Table 4-3. Signal Description (Sheet 6 of 8) Table 4-3. Signal Description (Sheet 7 of 8) Table 4-3. Signal Description (Sheet 8 of 8) Page 5 Design Considerations 5.1 Processor Thermal Specifications 5.1.1 Thermal Specifications Page Figure 5-1. Thermal Profile for the Pentium D Processor with PRB=1 Figure 5-2. Thermal Profile for the Pentium D Processor with PRB=0 5.1.2 Thermal Metrology 5.2 Processor Thermal Features 5.2.1 Thermal Monitor 5.2.2 On-Demand Mode 5.2.3 PROCHOT# Signal 5.2.4 FORCEPR# Signal Pin 5.2.5 THERMTRIP# Signal 5.2.6 TCONTROL and Fan Speed Reduction 5.2.7 Thermal Diode Page Page 6 6.1 Power-On Configuration Options 6.2 Clock Control and Low Power States 6.2.1 Normal State 6.2.2 HALT and Enhanced HALT Powerdown States 6.2.2.1 HALT Powerdown State 6.2.2.2 Enhanced HALT Powerdown State 6.2.3 Stop-Grant State 6.2.4 Enhanced HALT Snoop or HALT Snoop State, Grant Snoop State 6.2.4.1 HALT Snoop State, Grant Snoop State 6.2.4.2 Enhanced HALT Snoop State 6.2.5 Enhanced Intel SpeedStep Techn olo gy 7 7.1 Mechanical Specifications 7.1.1 Boxed Processor Cooling Solution Dimensions 7.1.2 Boxed Processor Fan Heatsink Weight 7.1.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly 7.2 Electrical Requirements 7.2.1 Fan Heatsink Power Supply Page 7.3 Thermal Specifications 7.3.1 Boxed Processor Cooling Requirements Page 7.3.2 Variable Speed Fan Page 8 (BTX) Type I Boxed Processor Specifications 8.1 Mechanical Specifications 8.1.1 Cooling Solution Dimensions 8.1.2 Boxed Processor Fan Heatsink Weight 8.1.3 Boxed Processor Support and Retention Module (SRM) 8.2 Electrical Requirements 8.2.1 Fan Heatsink Power Supply Page 8.3 Thermal Specifications 8.3.1 Boxed Processor Cooling Requirements 8.3.2 Variable Speed Fan Page Page 9 9.1 Logic Analyzer Interface (LAI) 9.1.1 Mechanical Considerations 9.1.2 Electrical Considerations