Intel 830 manual FSB DC Specifications, BSEL20 and VID50 Signal Group DC Specifications

Electrical Specifications

2.6.3FSB DC Specifications

The processor front side bus DC specifications in this section are defined at the processor core (pads) unless otherwise stated. All specifications apply to all frequencies and cache sizes unless otherwise stated.

Table 2-10. BSEL[2:0] and VID[5:0] Signal Group DC Specifications

Symbol	Parameter	Max	Unit	Notes1, 2
RON (BSEL)	Buffer On Resistance	60	Ω	-
RON (VID)	Buffer On Resistance	60	Ω	-
IOL	Max Land Current	8	mA	-
ILO	Output Leakage Current	200	µA	3
VTOL	Voltage Tolerance	VTT (max)	V	-

NOTES:

1.Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2.These parameters are not tested and are based on design simulations.

3.Leakage to VSS with land held at 2.5V.

Table 2-11. GTL+ Signal Group DC Specifications

Symbol	Parameter	Min	Max	Unit	Notes1
VIL	Input Low Voltage	0.0	GTLREF – (0.10 * VTT)	V	2,	3
VIH	Input High Voltage	GTLREF + (0.10 * VTT)	VTT	V	3, 4, 5
VOH	Output High Voltage	N/A	VTT	V	3, 5
IOL	Output Low Current	N/A	VTT/[(0.50*RTT_MIN) +	A	-
			RON_MIN]
ILI	Input Leakage Current	N/A	± 200	µA	6
ILO	Output Leakage	N/A	± 200	µA	6
	Current
RON	Buffer On Resistance	8	12	Ω
NOTES:

1.Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2.VIL is defined as the voltage range at a receiving agent that will be interpreted as a logical low value.

3.The VTT referred to in these specifications is the instantaneous VTT.

4.VIH is defined as the voltage range at a receiving agent that will be interpreted as a logical high value.

5.VIH and VOH may experience excursions above VTT.

6.Leakage to VSS with land held at VTT.

Datasheet 29