3. Status Enable Register
The Status Enable Register is set by the user to Enable SRQs for changes in power supply status.
Table
BIT | Status name | Status symbol | Bit Set condition | Bit reset condition | |
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0 (LSB) | Constant Voltage | CV |
| User command: “SENA nn” | |
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| User command: | is received, where nn is | |
1 | Constant Current | CC | |||
hexadecimal bits. | |||||
“SENA nn” is | |||||
2 | No Fault | NFLT | received, where | If “nn”=00, no SRQ is sent | |
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| nn is hexadecimal | when there is a change in | |
3 |
| FLT | |||
Fault active | bits. | Status Condition Register. | |||
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4 | AST | Always zero | Always zero | ||
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5 | Fold enabled | FDE | Always zero | Always zero | |
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6 | Spare | Spare | Always zero | Always zero | |
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7 (MSB) | Local Mode | LCL | “SENA nn” | “SENA nn” | |
command | command | ||||
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4. Status Event Register
The Status Event Register will set a bit if a change in the power supply status occurs and it is en- abled. The register is cleared when the “SEVE?” or “CLS” commands are received. A change in this register will generate SRQ.
Table
BIT | Status name | Status symbol | Bit Set condition | Bit reset condition | |
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0 (LSB) | Constant Voltage | CV | Changes in status |
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occur and it is |
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| Enabled. |
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1 | Constant Current | CC | The change can |
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| set a bit, but when |
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2 | No Fault | NFLT |
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the change clears | Entire Event Register is | ||||
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| the bit remains | cleared when user sends | |
3 | Fault active | FLT | |||
set. | “SEVE?” command to read | ||||
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4 | 0 | Always zero | the register. | ||
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| “CLS” and | |
5 | Fold enabled | 0 | Always zero | ||
clear the Status Event | |||||
6 | Spare | 0 | Always zero | Register. | |
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| Unit is set to Local |
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7 (MSB) | Local Mode | LCL | by pressing front |
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panel REM/LOC |
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| button. |
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