Texas Instruments MSP430x11x1 warranty Busy, Keyv, Accvifg, Wait

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MSP430x11x1

 

 

MIXED SIGNAL MICROCONTROLLER

 

 

SLAS241C ± SEPTEMBER 1999 ± REVISED JUNE 2000

 

 

 

flash memory control register FCTL3 (continued)

BUSY

012Ch, bit0,

The BUSY bit shows if an access to the flash memory is allowed (BUSY=0), or

 

 

if an access violation occurs. The BUSY bit is read-only, but a write operation is

 

 

allowed. The BUSY bit should be tested before each write and erase cycle. The

 

 

flash timing-generator hardware immediately sets the BUSY bit after start of a

 

 

write, segment-write, erase, or mass erase operation. If the timing generator has

 

 

completed the operation, the BUSY bit is reset by the hardware.

 

 

No program code can be executed from the busy flash memory during the entire

 

 

program or erase cycle.

 

 

0: Flash memory is not busy.

 

 

1: Flash memory is busy, and remains in busy state if segment write function

 

 

is in wait mode.

KEYV,

012Ch, bit1

Key violation

 

 

0: Key 0A5h (high byte) was not violated.

 

 

1: Key 0A5h (high byte) was violated. Violation occurs when a write access to

 

 

registers FCTL1, FCTL2, or FCTL3 is executed and the high byte is not

 

 

equal to 0A5h. If the security key is violated, bit KEYV is set and a PUC is

 

 

performed.

ACCVIFG,

012Ch, bit2

Access violation interrupt flag

 

 

The access-violation flag is set when any combination of control bits other than

 

 

those shown in Table 3 is attempted, or an instruction is fetched while a

 

 

segment-write operation is active.

 

 

Reading the control registers will not set the ACCVIFG bit.

 

 

NOTE: The respective interrupt-enable bit ACCVIE is located in the interrupt

 

 

enable register IE1 in the special function register. The software can set

 

 

the ACCVIFG bit. If set by software, an NMI is also executed.

WAIT,

012CH, bit3

In the segment-write mode, the WAIT bit indicates that data has been written and

 

 

the flash memory is prepared to receive the next data for programming. The

 

 

WAIT bit is read only, but a write to the WAIT bit is allowed.

0: The segment-write operation has began and programming is in progress.

1: The segment-write operation is active and data programming is complete.

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Contents MSP430x11x1 DescriptionTssop Pulldown resistor of 30 k Ω is needed on F11x1 Functional block diagramAvailable Options Packaged Devices PIN Sowb PIN TssopTerminal Description Name Terminal FunctionsShort-form description Processing unitInstruction Word Formats Address Mode DescriptionsCPU Instruction setOperation modes and interrupts Low-power consumption capabilitiesSCG1 SCG0 Status register R2SCG1 SCG0CCIFG1, CCIFG2, Taifg Interrupt vector addressesCaifg WdtifgNmiifg Special function registersWdtifg OfifgBoot ROM containing bootstrap loader Functions of the bootstrap loaderMemory organization VCC RST/NMI PIN Test PIN Features of the bootstrap loader areHardware resources used for serial input/output WDTInternal Bootstrap loader StartsVCC TestFlash memory control register FCTL1 Flash memoryFlash memory, timing generator, control register FCTL2 Erase 0128h, bit1, Erase a segmentWRT Aclk Flash memory control register FCTL3FN0±FN5 SSEL0, SSEL1Wait BusyKeyv AccvifgFlash memory, interrupt and security key violation LockEmex Nmirs AccvPUC POROscillator and system clock PeripheralsDigital I/O Clock SignalsTimerA Three capture/compare registers Watchdog timerTimerA, MSP430x11x1 Configuration TimerA 3 capture/compare registersComparatorA CATCTL2.7 CaoutCAF CACTL2.4CACTL2 Slope a/d conversionCACTL1 Caex Caon Caies Caifg Rsel REF1 REF0Peripherals with Word Access Peripherals with Byte AccessPeripheral file map Absolute maximum ratings² Recommended operating conditionsMIN NOM MAX Units Frequency vs Supply Voltage MSP430x11x1 DevicesILPM3 Parameter Test Conditions MIN TYP MAX UnitIAM ILPM2Leakage current Outputs Port 1 to P2 P1.0 to P1.7, P2.0 to P2.5Port P1, P2 P1.x to P2.x Internal signals TAx, Smclk at TimerAInputs Px.x, TAx Parameter Test Conditions VCC MIN TYP MAX UnitComparatorA see Note Outputs P1.x, P2.x, TAxVRefVT vs Temperature, VCC = 2.2 V, C1121 VRefVT vs Temperature, VCC = 3 V, C1121CAF Caon PUC/PORParameter MIN NOM MAX Unit RAMDCO Steps DCOVariance Max DcoclkPrinciple characteristics of the DCO Wake-up from lower power modes LPMxJTAG/programming Input/output schematic Port P1, P1.0 to P1.3, input/output with Schmitt-triggerGND P1IFG.5 P1IES.5 P1DIR.4 P1OUT.4 SmclkP1IFG.4 P1IES.4 P1DIR.5 P1OUT.5CAPD.X Port P2, P2.0 to P2.2, input/output with Schmitt-triggerP2DIR.4 P2OUT.4 Port P2, P2.3 to P2.4, input/output with Schmitt-triggerP2DIR.3 P2OUT.3 P2IFG.3 P1IES.3P2IRQ.5 P2SEL.5 VCCP2DIR.5 P2OUT.5Port P2, unbonded bits P2.6 and P2.7 PIN Shown Pins DIM MAXDW R-PDSO-G Plastic SMALL-OUTLINE Package15 NOM Gage Plane Seating Plane 20 MAX Pins ShownPins DIM MAX MIN PW R-PDSO-G Plastic SMALL-OUTLINE PackageImportant Notice