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| MSP430x11x1 | |
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| MIXED SIGNAL MICROCONTROLLER | |
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| SLAS241C ± SEPTEMBER 1999 ± REVISED JUNE 2000 | |
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flash memory control register FCTL3 (continued) | |||
BUSY | 012Ch, bit0, | The BUSY bit shows if an access to the flash memory is allowed (BUSY=0), or | |
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| if an access violation occurs. The BUSY bit is | |
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| allowed. The BUSY bit should be tested before each write and erase cycle. The | |
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| flash | |
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| write, | |
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| completed the operation, the BUSY bit is reset by the hardware. | |
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| No program code can be executed from the busy flash memory during the entire | |
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| program or erase cycle. | |
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| 0: Flash memory is not busy. | |
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| 1: Flash memory is busy, and remains in busy state if segment write function | |
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| is in wait mode. | |
KEYV, | 012Ch, bit1 | Key violation | |
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| 0: Key 0A5h (high byte) was not violated. | |
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| 1: Key 0A5h (high byte) was violated. Violation occurs when a write access to | |
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| registers FCTL1, FCTL2, or FCTL3 is executed and the high byte is not | |
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| equal to 0A5h. If the security key is violated, bit KEYV is set and a PUC is | |
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| performed. | |
ACCVIFG, | 012Ch, bit2 | Access violation interrupt flag | |
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| The | |
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| those shown in Table 3 is attempted, or an instruction is fetched while a | |
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| Reading the control registers will not set the ACCVIFG bit. | |
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| NOTE: The respective | |
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| enable register IE1 in the special function register. The software can set | |
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| the ACCVIFG bit. If set by software, an NMI is also executed. | |
WAIT, | 012CH, bit3 | In the | |
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| the flash memory is prepared to receive the next data for programming. The | |
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| WAIT bit is read only, but a write to the WAIT bit is allowed. |
0: The
1: The
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