Texas Instruments MSP430x11x1 warranty Status register R2, SCG1 SCG0, Gie

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MSP430x11x1

MIXED SIGNAL MICROCONTROLLER

SLAS241C ± SEPTEMBER 1999 ± REVISED JUNE 2000

status register R2

15

9

8

7

6

5

4

3

2

1

0

Reserved For Future

 

V

SCG1

SCG0

OscOff

CPUOff

GIE

N

Z

C

Enhancements

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

rw-0

 

rw-0

rw-0

rw-0

rw-0

rw-0

rw-0

rw-0

rw-0

rw-0

The bits CPUOff, SCG1, SCG0, and OscOff are the most important low-power control bits when the basic function of the system clock generator is established. They are pushed onto the stack whenever an interrupt is accepted and thereby saved so that the previous mode of operation can be retrieved after the interrupt request. During execution of an interrupt handler routine, the bits can be manipulated via indirect access of the data on the stack. That allows the program to resume execution in another power operating mode after the return from interrupt (RETI).

SCG1:

The clock signal SMCLK, used for peripherals, is enabled when bit SCG1 is reset or disabled if

 

the bit is set.

SCG0:

The dc-generator is active when SCG0 is reset. The dc-generator can be deactivated only if the

 

SCG0 bit is set and the DCOCLK signal is not used for MCLK or SMCLK. The current consumed

 

by the dc-generator defines the basic frequency of the DCOCLK. It is a dc current.

 

The clock signal DCOCLK is deactivated if it is not used for MCLK or SMCLK or if the SCG0 bit

 

is set. There are two situations when the SCG0 bit cannot switch off the DCOCLK signal:

 

1. DCOCLK frequency is used for MCLK (CPUOff=0 and SELM.1=0).

 

2. DCOCLK frequency is used for SMCLK (SCG1=0 and SELS=0).

 

NOTE:

 

When the current is switched off (SCG0=1) the start of the DCOCLK is delayed slightly. The delay

 

is in the ∝s-range (see device parameters for details).

OscOff:

The LFXT1 crystal oscillator is active when the OscOff bit is reset. The LFXT1 oscillator can only

 

be deactivated if the OscOff bit is set and it is not used for MCLK or SMCLK. The setup time to

 

start a crystal oscillation needs consideration when oscillator off option is used. Mask

 

programmable (ROM) devices can disable this feature so that the oscillator can never be switched

 

off by software.

CPUOff:

The clock signal MCLK, used for the CPU, is active when the CPUOff bit is reset or stopped if it

 

is set.

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Contents MSP430x11x1 DescriptionTssop PIN Sowb PIN Tssop Functional block diagramAvailable Options Packaged Devices Pulldown resistor of 30 k Ω is needed on F11x1Processing unit Terminal FunctionsShort-form description Terminal Description NameInstruction set Address Mode DescriptionsCPU Instruction Word FormatsLow-power consumption capabilities Operation modes and interruptsSCG0 Status register R2SCG1 SCG1 SCG0Wdtifg Interrupt vector addressesCaifg CCIFG1, CCIFG2, TaifgOfifg Special function registersWdtifg NmiifgBoot ROM containing bootstrap loader Functions of the bootstrap loaderMemory organization WDT Features of the bootstrap loader areHardware resources used for serial input/output VCC RST/NMI PIN Test PINTest Bootstrap loader StartsVCC InternalFlash memory Flash memory control register FCTL1Flash memory, timing generator, control register FCTL2 Erase 0128h, bit1, Erase a segmentWRT SSEL0, SSEL1 Flash memory control register FCTL3FN0±FN5 AclkAccvifg BusyKeyv WaitFlash memory, interrupt and security key violation LockEmex POR AccvPUC NmirsPeripherals Oscillator and system clockClock Signals Digital I/OWatchdog timer TimerA Three capture/compare registersTimerA 3 capture/compare registers TimerA, MSP430x11x1 ConfigurationComparatorA CACTL2.4 CaoutCAF CATCTL2.7Caex Caon Caies Caifg Rsel REF1 REF0 Slope a/d conversionCACTL1 CACTL2Peripherals with Word Access Peripherals with Byte AccessPeripheral file map Absolute maximum ratings² Recommended operating conditionsMIN NOM MAX Units MSP430x11x1 Devices Frequency vs Supply VoltageILPM2 Parameter Test Conditions MIN TYP MAX UnitIAM ILPM3Outputs Port 1 to P2 P1.0 to P1.7, P2.0 to P2.5 Leakage currentParameter Test Conditions VCC MIN TYP MAX Unit Internal signals TAx, Smclk at TimerAInputs Px.x, TAx Port P1, P2 P1.x to P2.xOutputs P1.x, P2.x, TAx ComparatorA see NoteVRefVT vs Temperature, VCC = 3 V, C1121 VRefVT vs Temperature, VCC = 2.2 V, C1121PUC/POR CAF CaonRAM Parameter MIN NOM MAX UnitDcoclk DCOVariance Max DCO StepsPrinciple characteristics of the DCO Wake-up from lower power modes LPMxJTAG/programming Input/output schematic Port P1, P1.0 to P1.3, input/output with Schmitt-triggerGND P1DIR.5 P1OUT.5 P1DIR.4 P1OUT.4 SmclkP1IFG.4 P1IES.4 P1IFG.5 P1IES.5Port P2, P2.0 to P2.2, input/output with Schmitt-trigger CAPD.XP2IFG.3 P1IES.3 Port P2, P2.3 to P2.4, input/output with Schmitt-triggerP2DIR.3 P2OUT.3 P2DIR.4 P2OUT.4P2OUT.5 P2SEL.5 VCCP2DIR.5 P2IRQ.5Port P2, unbonded bits P2.6 and P2.7 Plastic SMALL-OUTLINE Package Pins DIM MAXDW R-PDSO-G PIN ShownPW R-PDSO-G Plastic SMALL-OUTLINE Package Pins ShownPins DIM MAX MIN 15 NOM Gage Plane Seating Plane 20 MAXImportant Notice
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