Texas Instruments MSP430x11x1 warranty P1DIR.4 P1OUT.4 Smclk, P1IFG.4 P1IES.4, P1DIR.5 P1OUT.5

Page 38

MSP430x11x1

MIXED SIGNAL MICROCONTROLLER

SLAS241C ± SEPTEMBER 1999 ± REVISED JUNE 2000

APPLICATION INFORMATION

Port P1, P1.4 to P1.7, input/output with Schmitt-trigger and in-system access features

P1SEL.x

 

VCC

0

 

P1DIR.x

 

 

See Note 27

 

 

Direction Control

1

 

 

 

From Module

0

See Note 28

P1OUT.x

Pad Logic

 

 

1

P1.4±P1.7

Module X OUT

 

 

 

 

 

See Note 28

See Note 27

 

GND

 

TST

P1IN.x

Bus Keeper

 

 

EN

Module X IN

D

 

 

 

 

 

 

 

TST

 

 

 

TEST

 

 

 

P1IRQ.x

P1IE.x

 

 

 

 

 

 

 

 

 

 

 

Interrupt

 

Fuse

 

 

60 kΩ

 

 

 

 

 

 

EN

 

 

 

 

 

 

 

 

Q

Edge

 

 

 

Typical

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P1IFG.x

Set

Select

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GND

 

 

 

 

 

 

 

 

 

 

Fuse

 

 

 

 

 

 

Interrupt

P1IES.x

Control By JTAG

 

 

 

 

 

 

 

Flag

 

Blow

 

NOTE: Fuse not implemented

 

 

 

 

 

 

 

 

 

 

 

 

 

P1SEL.x

 

Control

in F11x1

 

 

 

 

 

 

 

 

 

 

 

 

P1.x

 

 

 

 

 

 

 

TDO

 

 

 

 

 

 

 

 

 

 

 

 

Controlled By JTAG

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P1.7/TDI/TDO

 

 

 

 

 

Controlled by JTAG

 

 

 

 

 

 

 

 

 

 

 

 

TDI

 

TST

 

P1.x

 

 

 

 

 

 

 

 

 

 

 

 

P1.6/TDI

 

 

NOTE: The test pin should be protected from potential EMI

 

 

TST

 

P1.x

 

 

and ESD voltage spikes. This may require a smaller

TMS

 

 

 

 

 

 

 

 

 

 

 

external pulldown resistor in some applications.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P1.5/TMS

 

 

x = Bit identifier, 4 to 7 for port P1

 

 

 

 

 

 

 

 

 

During programming activity and during blowing

TCK

 

TST

 

P1.x

 

 

the fuse, the pin TDO/TDI is used to apply the test

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

input for JTAG circuitry.

 

 

 

 

 

 

 

P1.4/TCK

 

 

 

 

Direction

 

 

 

 

 

 

 

 

 

 

PnSel.x

PnDIR.x

control from

PnOUT.x

Module X OUT

PnIN.x

Module X IN

 

 

PnIE.x

PnIFG.x

PnIES.x

 

 

module

 

 

 

 

 

 

 

 

 

 

P1Sel.4

P1DIR.4

P1DIR.4

P1OUT.4

SMCLK

P1IN.4

unused

 

 

P1IE.4

P1IFG.4

P1IES.4

P1Sel.5

P1DIR.5

P1DIR.5

P1OUT.5

Out0 signal²

P1IN.5

unused

 

 

P1IE.5

P1IFG.5

P1IES.5

P1Sel.6

P1DIR.6

P1DIR.6

P1OUT.6

Out1 signal²

P1IN.6

unused

 

 

P1IE.6

P1IFG.6

P1IES.6

P1Sel.7

P1DIR.7

P1DIR.7

P1OUT.7

Out2 signal²

P1IN.7

unused

 

 

P1IE.7

P1IFG.7

P1IES.7

² Signal from or to Timer_A

NOTES: 27. Optional selection of pullup or pulldown resistors with ROM (masked) versions.

28. Fuses for optional pullup and pulldown resistors can only be programmed at the factory (ROM versions only).

38

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Image 38
Contents Tssop MSP430x11x1Description PIN Sowb PIN Tssop Functional block diagramAvailable Options Packaged Devices Pulldown resistor of 30 k Ω is needed on F11x1Processing unit Terminal FunctionsShort-form description Terminal Description NameInstruction set Address Mode DescriptionsCPU Instruction Word FormatsLow-power consumption capabilities Operation modes and interruptsSCG0 Status register R2SCG1 SCG1 SCG0Wdtifg Interrupt vector addressesCaifg CCIFG1, CCIFG2, TaifgOfifg Special function registersWdtifg NmiifgMemory organization Boot ROM containing bootstrap loaderFunctions of the bootstrap loader WDT Features of the bootstrap loader areHardware resources used for serial input/output VCC RST/NMI PIN Test PINTest Bootstrap loader StartsVCC InternalFlash memory Flash memory control register FCTL1WRT Flash memory, timing generator, control register FCTL2Erase 0128h, bit1, Erase a segment SSEL0, SSEL1 Flash memory control register FCTL3FN0±FN5 AclkAccvifg BusyKeyv WaitEmex Flash memory, interrupt and security key violationLock POR AccvPUC NmirsPeripherals Oscillator and system clockClock Signals Digital I/OWatchdog timer TimerA Three capture/compare registersTimerA 3 capture/compare registers TimerA, MSP430x11x1 ConfigurationComparatorA CACTL2.4 CaoutCAF CATCTL2.7Caex Caon Caies Caifg Rsel REF1 REF0 Slope a/d conversionCACTL1 CACTL2Peripheral file map Peripherals with Word AccessPeripherals with Byte Access MIN NOM MAX Units Absolute maximum ratings²Recommended operating conditions MSP430x11x1 Devices Frequency vs Supply VoltageILPM2 Parameter Test Conditions MIN TYP MAX UnitIAM ILPM3Outputs Port 1 to P2 P1.0 to P1.7, P2.0 to P2.5 Leakage currentParameter Test Conditions VCC MIN TYP MAX Unit Internal signals TAx, Smclk at TimerAInputs Px.x, TAx Port P1, P2 P1.x to P2.xOutputs P1.x, P2.x, TAx ComparatorA see NoteVRefVT vs Temperature, VCC = 3 V, C1121 VRefVT vs Temperature, VCC = 2.2 V, C1121PUC/POR CAF CaonRAM Parameter MIN NOM MAX UnitDcoclk DCOVariance Max DCO StepsJTAG/programming Principle characteristics of the DCOWake-up from lower power modes LPMx GND Input/output schematicPort P1, P1.0 to P1.3, input/output with Schmitt-trigger P1DIR.5 P1OUT.5 P1DIR.4 P1OUT.4 SmclkP1IFG.4 P1IES.4 P1IFG.5 P1IES.5Port P2, P2.0 to P2.2, input/output with Schmitt-trigger CAPD.XP2IFG.3 P1IES.3 Port P2, P2.3 to P2.4, input/output with Schmitt-triggerP2DIR.3 P2OUT.3 P2DIR.4 P2OUT.4P2OUT.5 P2SEL.5 VCCP2DIR.5 P2IRQ.5Port P2, unbonded bits P2.6 and P2.7 Plastic SMALL-OUTLINE Package Pins DIM MAXDW R-PDSO-G PIN ShownPW R-PDSO-G Plastic SMALL-OUTLINE Package Pins ShownPins DIM MAX MIN 15 NOM Gage Plane Seating Plane 20 MAXImportant Notice