Texas Instruments MSP430x11x1 P2SEL.5 VCC, P2DIR.5, P2OUT.5, P2IRQ.5, P2IFG.5, P2IES.5, CAPD.5

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MSP430x11x1

MIXED SIGNAL MICROCONTROLLER

SLAS241C ± SEPTEMBER 1999 ± REVISED JUNE 2000

Port P2, P2.5, input/output with Schmitt-trigger and ROSC function for the Basic Clock module

	P2SEL.5			VCC
	P2SEL.5	0	0: Input	Pad Logic
			0: Input
	P2DIR.5		1: Output
	P2DIR.5		1: Output	See Note 27
	Direction Control	1
	Direction Control
	From Module	0		See Note 28
	P2OUT.5	0		P2.5
	P2OUT.5			P2.5
	Module X OUT	1
	Module X OUT
				See Note 28
				See Note 27
				GND
	P2IN.5			Bus Keeper

	EN
Module X IN	D					Internal to
						Internal to
						Basic Clock
P2IRQ.5	P2IE.5		Interrupt			Module	1
		EN	Interrupt		VCC	0	1
		EN	Edge		VCC
	P2IFG.5	Q	Edge
	P2IFG.5	Set	Select
		Set
		Interrupt	P2IES.5			DC
		Flag	P2IES.5	DCOR
		Flag		DCOR
			P2SEL.5			Generator
			P2SEL.5
				CAPD.5

NOTE: DCOR: Control bit from Basic Clock Module if it is set, P2.5 Is disconnected from P2.5 pad

			Direction
PnSel.x		PnDIR.x	control from	PnOUT.x	Module X OUT	PnIN.x	Module X IN	PnIE.x	PnIFG.x	PnIES.x
			module

P2Sel.5		P2DIR.5	P2DIR.5	P2OUT.5	VSS	P2IN.5	unused	P2IE.5	P2IFG.5	P2IES.5
NOTES: 27.		Optional selection of pullup or pulldown resistors with ROM (masked) versions.
28.		Fuses for optional pullup and pulldown resistors can only be programmed at the factory (ROM versions only).

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Contents Tssop MSP430x11x1Description Available Options Packaged Devices Functional block diagramPIN Sowb PIN Tssop Pulldown resistor of 30 k Ω is needed on F11x1Short-form description Terminal FunctionsProcessing unit Terminal Description NameCPU Address Mode DescriptionsInstruction set Instruction Word FormatsOperation modes and interrupts Low-power consumption capabilitiesSCG1 Status register R2SCG0 SCG1 SCG0Caifg Interrupt vector addressesWdtifg CCIFG1, CCIFG2, TaifgWdtifg Special function registersOfifg NmiifgMemory organization Boot ROM containing bootstrap loaderFunctions of the bootstrap loader Hardware resources used for serial input/output Features of the bootstrap loader areWDT VCC RST/NMI PIN Test PINVCC Bootstrap loader StartsTest InternalFlash memory control register FCTL1 Flash memoryWRT Flash memory, timing generator, control register FCTL2Erase 0128h, bit1, Erase a segment FN0±FN5 Flash memory control register FCTL3SSEL0, SSEL1 AclkKeyv BusyAccvifg WaitEmex Flash memory, interrupt and security key violationLock PUC AccvPOR NmirsOscillator and system clock PeripheralsDigital I/O Clock SignalsTimerA Three capture/compare registers Watchdog timerTimerA, MSP430x11x1 Configuration TimerA 3 capture/compare registersComparatorA CAF CaoutCACTL2.4 CATCTL2.7CACTL1 Slope a/d conversionCaex Caon Caies Caifg Rsel REF1 REF0 CACTL2Peripheral file map Peripherals with Word AccessPeripherals with Byte Access MIN NOM MAX Units Absolute maximum ratings²Recommended operating conditions Frequency vs Supply Voltage MSP430x11x1 DevicesIAM Parameter Test Conditions MIN TYP MAX UnitILPM2 ILPM3Leakage current Outputs Port 1 to P2 P1.0 to P1.7, P2.0 to P2.5Inputs Px.x, TAx Internal signals TAx, Smclk at TimerAParameter Test Conditions VCC MIN TYP MAX Unit Port P1, P2 P1.x to P2.xComparatorA see Note Outputs P1.x, P2.x, TAxVRefVT vs Temperature, VCC = 2.2 V, C1121 VRefVT vs Temperature, VCC = 3 V, C1121CAF Caon PUC/PORParameter MIN NOM MAX Unit RAMVariance Max DCODcoclk DCO StepsJTAG/programming Principle characteristics of the DCOWake-up from lower power modes LPMx GND Input/output schematicPort P1, P1.0 to P1.3, input/output with Schmitt-trigger P1IFG.4 P1IES.4 P1DIR.4 P1OUT.4 SmclkP1DIR.5 P1OUT.5 P1IFG.5 P1IES.5CAPD.X Port P2, P2.0 to P2.2, input/output with Schmitt-triggerP2DIR.3 P2OUT.3 Port P2, P2.3 to P2.4, input/output with Schmitt-triggerP2IFG.3 P1IES.3 P2DIR.4 P2OUT.4P2DIR.5 P2SEL.5 VCCP2OUT.5 P2IRQ.5Port P2, unbonded bits P2.6 and P2.7 DW R-PDSO-G Pins DIM MAXPlastic SMALL-OUTLINE Package PIN ShownPins DIM MAX MIN Pins ShownPW R-PDSO-G Plastic SMALL-OUTLINE Package 15 NOM Gage Plane Seating Plane 20 MAXImportant Notice