Texas Instruments MSP430x11x1 warranty Peripheral file map, Peripherals with Word Access

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MSP430x11x1

MIXED SIGNAL MICROCONTROLLER

SLAS241C ± SEPTEMBER 1999 ± REVISED JUNE 2000

peripheral file map

PERIPHERALS WITH WORD ACCESS

Timer_A		Reserved			017Eh
		Reserved			017Ch
		Reserved			017Ah
		Reserved			0178h
		Capture/compare register		CCR2	0176h
		Capture/compare register		CCR1	0174h
		Capture/compare register		CCR0	0172h
		Timer_A register		TAR	0170h
		Reserved			016Eh
		Reserved			016Ch
		Reserved			016Ah
		Reserved			0168h
		Capture/compare control		CCTL2	0166h
		Capture/compare control		CCTL1	0164h
		Capture/compare control		CCTL0	0162h
		Timer_A control		TACTL	0160h
		Timer_A interrupt vector		TAIV	012Eh

Flash Memory		Flash control 3		FCTL3	012Ch
		Flash control 2		FCTL2	012Ah
		Flash control 1		FCTL1	0128h

Watchdog		Watchdog/timer control		WDTCTL	0120h


	PERIPHERALS WITH BYTE ACCESS

Comparator_A		Comparator_A port disable		CAPD	05Bh
		Comparator_A control2		CACTL2	05Ah
		Comparator_A control1		CACTL1	059h

System Clock		Basic clock sys. control2		BCSCTL2	058h
		Basic clock sys. control1		BCSCTL1	057h
		DCO clock freq. control		DCOCTL	056h

Port P2		Port P2 selection		P2SEL	02Eh
		Port P2 interrupt enable		P2IE	02Dh
		Port P2 interrupt edge select		P2IES	02Ch
		Port P2 interrupt flag		P2IFG	02Bh
		Port P2 direction		P2DIR	02Ah
		Port P2 output		P2OUT	029h
		Port P2 input		P2IN	028h

Port P1		Port P1 selection		P1SEL	026h
		Port P1 interrupt enable		P1IE	025h
		Port P1 interrupt edge select		P1IES	024h
		Port P1 interrupt flag		P1IFG	023h
		Port P1 direction		P1DIR	022h
		Port P1 output		P1OUT	021h
		Port P1 input		P1IN	020h

Special Function		SFR interrupt flag2		IFG2	003h
		SFR interrupt flag1		IFG1	002h
		SFR interrupt enable2		IE2	001h
		SFR interrupt enable1		IE1	000h

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Contents Description MSP430x11x1Tssop Available Options Packaged Devices Functional block diagramPIN Sowb PIN Tssop Pulldown resistor of 30 k Ω is needed on F11x1Short-form description Terminal FunctionsProcessing unit Terminal Description NameCPU Address Mode DescriptionsInstruction set Instruction Word FormatsOperation modes and interrupts Low-power consumption capabilitiesSCG1 Status register R2SCG0 SCG1 SCG0Caifg Interrupt vector addressesWdtifg CCIFG1, CCIFG2, TaifgWdtifg Special function registersOfifg NmiifgFunctions of the bootstrap loader Boot ROM containing bootstrap loaderMemory organization Hardware resources used for serial input/output Features of the bootstrap loader areWDT VCC RST/NMI PIN Test PINVCC Bootstrap loader StartsTest InternalFlash memory control register FCTL1 Flash memoryErase 0128h, bit1, Erase a segment Flash memory, timing generator, control register FCTL2WRT FN0±FN5 Flash memory control register FCTL3SSEL0, SSEL1 AclkKeyv BusyAccvifg WaitLock Flash memory, interrupt and security key violationEmex PUC AccvPOR NmirsOscillator and system clock PeripheralsDigital I/O Clock SignalsTimerA Three capture/compare registers Watchdog timerTimerA, MSP430x11x1 Configuration TimerA 3 capture/compare registersComparatorA CAF CaoutCACTL2.4 CATCTL2.7CACTL1 Slope a/d conversionCaex Caon Caies Caifg Rsel REF1 REF0 CACTL2Peripherals with Byte Access Peripherals with Word AccessPeripheral file map Recommended operating conditions Absolute maximum ratings²MIN NOM MAX Units Frequency vs Supply Voltage MSP430x11x1 DevicesIAM Parameter Test Conditions MIN TYP MAX UnitILPM2 ILPM3Leakage current Outputs Port 1 to P2 P1.0 to P1.7, P2.0 to P2.5Inputs Px.x, TAx Internal signals TAx, Smclk at TimerAParameter Test Conditions VCC MIN TYP MAX Unit Port P1, P2 P1.x to P2.xComparatorA see Note Outputs P1.x, P2.x, TAxVRefVT vs Temperature, VCC = 2.2 V, C1121 VRefVT vs Temperature, VCC = 3 V, C1121CAF Caon PUC/PORParameter MIN NOM MAX Unit RAMVariance Max DCODcoclk DCO StepsWake-up from lower power modes LPMx Principle characteristics of the DCOJTAG/programming Port P1, P1.0 to P1.3, input/output with Schmitt-trigger Input/output schematicGND P1IFG.4 P1IES.4 P1DIR.4 P1OUT.4 SmclkP1DIR.5 P1OUT.5 P1IFG.5 P1IES.5CAPD.X Port P2, P2.0 to P2.2, input/output with Schmitt-triggerP2DIR.3 P2OUT.3 Port P2, P2.3 to P2.4, input/output with Schmitt-triggerP2IFG.3 P1IES.3 P2DIR.4 P2OUT.4P2DIR.5 P2SEL.5 VCCP2OUT.5 P2IRQ.5Port P2, unbonded bits P2.6 and P2.7 DW R-PDSO-G Pins DIM MAXPlastic SMALL-OUTLINE Package PIN ShownPins DIM MAX MIN Pins ShownPW R-PDSO-G Plastic SMALL-OUTLINE Package 15 NOM Gage Plane Seating Plane 20 MAXImportant Notice