Texas Instruments MSP430x11x1 warranty Terminal Functions, Short-form description, Processing unit

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MSP430x11x1

 

 

 

 

 

MIXED SIGNAL MICROCONTROLLER

 

 

 

 

 

SLAS241C ± SEPTEMBER 1999 ± REVISED JUNE 2000

 

 

 

 

 

 

 

 

 

 

 

 

Terminal Functions

 

 

 

 

 

 

 

 

 

TERMINAL

 

I/O

DESCRIPTION

 

 

 

NAME

NO.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P1.0/TACLK

13

I/O

General-purpose digital I/O pin/Timer_A, clock signal TACLK input

 

 

 

 

 

 

 

 

 

P1.1/TA0

14

I/O

General-purpose digital I/O pin/Timer_A, capture: CCI0A input, compare: Out0 output

 

 

 

 

 

 

 

 

 

P1.2/TA1

15

I/O

General-purpose digital I/O pin/Timer_A, capture: CCI1A input, compare: Out1 output

 

 

 

 

 

 

 

 

 

P1.3/TA2

16

I/O

General-purpose digital I/O pin/Timer_A, capture: CCI2A input, compare: Out2 output

 

 

 

 

 

 

 

 

 

P1.4/SMCLK/TCK

17

I/O

General-purpose digital I/O pin/SMCLK signal output/test clock, input terminal for device programming

 

 

 

 

 

 

and test

 

 

 

 

 

 

 

 

 

P1.5/TA0/TMS

18

I/O

General-purpose digital I/O pin/Timer_A, compare: Out0 output/test mode select, input terminal for

 

 

 

 

 

 

device programming and test

 

 

 

 

 

 

 

 

 

P1.6/TA1/TDI

19

I/O

General-purpose digital I/O pin/Timer_A, compare: Out1 output/test data input terminal

 

 

 

 

 

 

 

 

 

P1.7/TA2/TDO/TDI²

20

I/O

General-purpose digital I/O pin/Timer_A, compare: Out2 output/test data output terminal or data input

 

 

 

 

 

 

during programming

 

 

 

 

 

 

 

 

 

P2.0/ACLK

8

I/O

General-purpose digital I/O pin/ACLK output

 

 

 

 

 

 

 

 

 

P2.1/INCLK

9

I/O

General-purpose digital I/O pin/Timer_A, clock signal at INCLK

 

 

 

 

 

 

 

 

 

P2.2/CAOUT/TA0

10

I/O

General-purpose digital I/O pin/Timer_A, capture: CCI0B input/comparator_A, output

 

 

 

 

 

 

 

 

 

P2.3/CA0/TA1

11

I/O

General-purpose digital I/O pin/Timer_A, compare: Out1 output/comparator_A, input

 

 

 

 

 

 

 

 

 

P2.4/CA1/TA2

12

I/O

General-purpose digital I/O pin/Timer_A, compare: Out2 output/comparator_A, input

 

 

 

 

 

 

 

 

 

P2.5/Rosc

3

I/O

General-purpose digital I/O pin/Input for external resistor that defines the DCO nominal frequency

 

 

 

 

7

I

Reset or nonmaskable interrupt input

 

 

RST/NMI

 

 

 

 

 

 

 

 

TEST

1

I

Select of test mode for JTAG pins on Port1. Must be tied low with less than 30 kΩ (F11x1).

 

 

 

 

 

 

 

 

VCC

2

 

Supply voltage

 

 

 

 

 

 

 

 

VSS

4

 

Ground reference

 

 

XIN

6

I

Input terminal of crystal oscillator

 

 

 

 

 

 

 

 

XOUT

5

I/O

Output terminal of crystal oscillator

 

² TDO or TDI is selected via JTAG instruction.

short-form description

processing unit

The processing unit is based on a consistent, and orthogonally-designed CPU and instruction set. This design structure results in a RISC-like architecture, highly transparent to the application development, and noted for its programming simplicity. All operations other than program-flow instructions are consequently performed as register operations in conjunction with seven addressing modes for source, and four modes for destination operands.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

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Contents MSP430x11x1 DescriptionTssop Pulldown resistor of 30 k Ω is needed on F11x1 Functional block diagramAvailable Options Packaged Devices PIN Sowb PIN TssopTerminal Description Name Terminal FunctionsShort-form description Processing unitInstruction Word Formats Address Mode DescriptionsCPU Instruction setOperation modes and interrupts Low-power consumption capabilitiesSCG1 SCG0 Status register R2SCG1 SCG0CCIFG1, CCIFG2, Taifg Interrupt vector addressesCaifg WdtifgNmiifg Special function registersWdtifg OfifgBoot ROM containing bootstrap loader Functions of the bootstrap loaderMemory organization VCC RST/NMI PIN Test PIN Features of the bootstrap loader areHardware resources used for serial input/output WDTInternal Bootstrap loader StartsVCC TestFlash memory control register FCTL1 Flash memoryFlash memory, timing generator, control register FCTL2 Erase 0128h, bit1, Erase a segmentWRT Aclk Flash memory control register FCTL3FN0±FN5 SSEL0, SSEL1Wait BusyKeyv AccvifgFlash memory, interrupt and security key violation LockEmex Nmirs AccvPUC POROscillator and system clock PeripheralsDigital I/O Clock SignalsTimerA Three capture/compare registers Watchdog timerTimerA, MSP430x11x1 Configuration TimerA 3 capture/compare registersComparatorA CATCTL2.7 CaoutCAF CACTL2.4CACTL2 Slope a/d conversionCACTL1 Caex Caon Caies Caifg Rsel REF1 REF0Peripherals with Word Access Peripherals with Byte AccessPeripheral file map Absolute maximum ratings² Recommended operating conditionsMIN NOM MAX Units Frequency vs Supply Voltage MSP430x11x1 DevicesILPM3 Parameter Test Conditions MIN TYP MAX UnitIAM ILPM2Leakage current Outputs Port 1 to P2 P1.0 to P1.7, P2.0 to P2.5Port P1, P2 P1.x to P2.x Internal signals TAx, Smclk at TimerAInputs Px.x, TAx Parameter Test Conditions VCC MIN TYP MAX UnitComparatorA see Note Outputs P1.x, P2.x, TAxVRefVT vs Temperature, VCC = 2.2 V, C1121 VRefVT vs Temperature, VCC = 3 V, C1121CAF Caon PUC/PORParameter MIN NOM MAX Unit RAMDCO Steps DCOVariance Max DcoclkPrinciple characteristics of the DCO Wake-up from lower power modes LPMxJTAG/programming Input/output schematic Port P1, P1.0 to P1.3, input/output with Schmitt-triggerGND P1IFG.5 P1IES.5 P1DIR.4 P1OUT.4 SmclkP1IFG.4 P1IES.4 P1DIR.5 P1OUT.5CAPD.X Port P2, P2.0 to P2.2, input/output with Schmitt-triggerP2DIR.4 P2OUT.4 Port P2, P2.3 to P2.4, input/output with Schmitt-triggerP2DIR.3 P2OUT.3 P2IFG.3 P1IES.3P2IRQ.5 P2SEL.5 VCCP2DIR.5 P2OUT.5Port P2, unbonded bits P2.6 and P2.7 PIN Shown Pins DIM MAXDW R-PDSO-G Plastic SMALL-OUTLINE Package15 NOM Gage Plane Seating Plane 20 MAX Pins ShownPins DIM MAX MIN PW R-PDSO-G Plastic SMALL-OUTLINE PackageImportant Notice
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