Texas Instruments MSP430x11x1 Dw R-Pdso-G, Plastic SMALL-OUTLINE Package, PIN Shown, Pins DIM MAX

Page 43

MSP430x11x1

MIXED SIGNAL MICROCONTROLLER

SLAS241C ± SEPTEMBER 1999 ± REVISED JUNE 2000

MECHANICAL DATA

DW (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

16 PIN SHOWN
0.050 (1,27)	0.020 (0,51)	0.010 (0,25)		M
	0.014 (0,35)	0.010 (0,25)		M
	0.014 (0,35)
16	9
		0.419 (10,65)
		0.400 (10,15)
	0.299 (7,59)				0.010 (0,25) NOM
	0.293 (7,45)
					Gage Plane
						0.010 (0,25)
1	8				0°± 8°	0.050 (1,27)
	A				0°± 8°	0.050 (1,27)
	A					0.016 (0,40)
						0.016 (0,40)
		Seating Plane
0.104 (2,65) MAX	0.012 (0,30)	0.004 (0,10)
	0.004 (0,10)	0.004 (0,10)


	PINS **	16	20		24
	DIM	16	20		24
	DIM
	A MAX	0.410	0.510		0.610
	A MAX	(10,41)	(12,95)		(15,49)
		(10,41)	(12,95)		(15,49)
	A MIN	0.400	0.500		0.600
	A MIN	(10,16)	(12,70)		(15,24)
		(10,16)	(12,70)		(15,24)
						4040000/ D 02/98

NOTES: A. All linear dimensions are in inches (millimeters).

B.This drawing is subject to change without notice.

C.Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).

D.Falls within JEDEC MS-013

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

Image 43

Contents Description MSP430x11x1Tssop Pulldown resistor of 30 k Ω is needed on F11x1 Functional block diagramAvailable Options Packaged Devices PIN Sowb PIN TssopTerminal Description Name Terminal FunctionsShort-form description Processing unitInstruction Word Formats Address Mode DescriptionsCPU Instruction setOperation modes and interrupts Low-power consumption capabilitiesSCG1 SCG0 Status register R2SCG1 SCG0CCIFG1, CCIFG2, Taifg Interrupt vector addressesCaifg WdtifgNmiifg Special function registersWdtifg OfifgFunctions of the bootstrap loader Boot ROM containing bootstrap loaderMemory organization VCC RST/NMI PIN Test PIN Features of the bootstrap loader areHardware resources used for serial input/output WDTInternal Bootstrap loader StartsVCC TestFlash memory control register FCTL1 Flash memoryErase 0128h, bit1, Erase a segment Flash memory, timing generator, control register FCTL2WRT Aclk Flash memory control register FCTL3FN0±FN5 SSEL0, SSEL1Wait BusyKeyv AccvifgLock Flash memory, interrupt and security key violationEmex Nmirs AccvPUC POROscillator and system clock PeripheralsDigital I/O Clock SignalsTimerA Three capture/compare registers Watchdog timerTimerA, MSP430x11x1 Configuration TimerA 3 capture/compare registersComparatorA CATCTL2.7 CaoutCAF CACTL2.4CACTL2 Slope a/d conversionCACTL1 Caex Caon Caies Caifg Rsel REF1 REF0Peripherals with Byte Access Peripherals with Word AccessPeripheral file map Recommended operating conditions Absolute maximum ratings²MIN NOM MAX Units Frequency vs Supply Voltage MSP430x11x1 DevicesILPM3 Parameter Test Conditions MIN TYP MAX UnitIAM ILPM2Leakage current Outputs Port 1 to P2 P1.0 to P1.7, P2.0 to P2.5Port P1, P2 P1.x to P2.x Internal signals TAx, Smclk at TimerAInputs Px.x, TAx Parameter Test Conditions VCC MIN TYP MAX UnitComparatorA see Note Outputs P1.x, P2.x, TAxVRefVT vs Temperature, VCC = 2.2 V, C1121 VRefVT vs Temperature, VCC = 3 V, C1121CAF Caon PUC/PORParameter MIN NOM MAX Unit RAMDCO Steps DCOVariance Max DcoclkWake-up from lower power modes LPMx Principle characteristics of the DCOJTAG/programming Port P1, P1.0 to P1.3, input/output with Schmitt-trigger Input/output schematicGND P1IFG.5 P1IES.5 P1DIR.4 P1OUT.4 SmclkP1IFG.4 P1IES.4 P1DIR.5 P1OUT.5CAPD.X Port P2, P2.0 to P2.2, input/output with Schmitt-triggerP2DIR.4 P2OUT.4 Port P2, P2.3 to P2.4, input/output with Schmitt-triggerP2DIR.3 P2OUT.3 P2IFG.3 P1IES.3P2IRQ.5 P2SEL.5 VCCP2DIR.5 P2OUT.5Port P2, unbonded bits P2.6 and P2.7 PIN Shown Pins DIM MAXDW R-PDSO-G Plastic SMALL-OUTLINE Package15 NOM Gage Plane Seating Plane 20 MAX Pins ShownPins DIM MAX MIN PW R-PDSO-G Plastic SMALL-OUTLINE PackageImportant Notice

MIXED SIGNAL MICROCONTROLLER

MECHANICAL DATA

DW (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

16 PIN SHOWN

PINS **

DIM

A MAX

0.400

0.500

0.600

(10,16)

(12,70)

(15,24)