Texas Instruments MSP430x11x1 warranty Input/output schematic, Gnd

Page 37

MSP430x11x1

MIXED SIGNAL MICROCONTROLLER

SLAS241C ± SEPTEMBER 1999 ± REVISED JUNE 2000

APPLICATION INFORMATION

input/output schematic

Port P1, P1.0 to P1.3, input/output with Schmitt-trigger

P1SEL.x

P1DIR.x

Direction Control From Module

P1OUT.x

Module X OUT

P1IN.x

			VCC
	0		(See Note 27)
	1
	0		(See Note 28)
	0	Pad Logic	P1.0 ± P1.3
		Pad Logic	P1.0 ± P1.3
	1
			(See Note 28)
			(See Note 27)

Module X IN

EN

D

GND

P1IRQ.x

	P1IE.x	EN			Interrupt
					Interrupt
					Edge
		Q
	P1IFG.x	Q
		Set			Select
		Set			Select

Interrupt

FlagP1IES.x

P1SEL.x

NOTE: x = Bit/identifier, 0 to 3 for port P1

		Direction
PnSel.x	PnDIR.x	control from	PnOUT.x	Module X OUT	PnIN.x	Module X IN	PnIE.x	PnIFG.x	PnIES.x
		module

P1Sel.0	P1DIR.0	P1DIR.0	P1OUT.0	VSS	P1IN.0	TACLK²	P1IE.0	P1IFG.0	P1IES.0
P1Sel.1	P1DIR.1	P1DIR.1	P1OUT.1	Out0 signal²	P1IN.1	CCI0A²	P1IE.1	P1IFG.1	P1IES.1
P1Sel.2	P1DIR.2	P1DIR.2	P1OUT.2	Out1 signal²	P1IN.2	CCI1A²	P1IE.2	P1IFG.2	P1IES.2
P1Sel.3	P1DIR.3	P1DIR.3	P1OUT.3	Out2 signal²	P1IN.3	CCI2A²	P1IE.3	P1IFG.3	P1IES.3

²Signal from or to Timer_A

NOTES: 27. Optional selection of pullup or pulldown resistors with ROM (masked) versions.

28. Fuses for optional pullup and pulldown resistors can only be programmed at the factory (ROM versions only).

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

37

Image 37

Contents Description MSP430x11x1Tssop Available Options Packaged Devices Functional block diagramPIN Sowb PIN Tssop Pulldown resistor of 30 k Ω is needed on F11x1Short-form description Terminal FunctionsProcessing unit Terminal Description NameCPU Address Mode DescriptionsInstruction set Instruction Word FormatsOperation modes and interrupts Low-power consumption capabilitiesSCG1 Status register R2SCG0 SCG1 SCG0Caifg Interrupt vector addressesWdtifg CCIFG1, CCIFG2, TaifgWdtifg Special function registersOfifg NmiifgFunctions of the bootstrap loader Boot ROM containing bootstrap loaderMemory organization Hardware resources used for serial input/output Features of the bootstrap loader areWDT VCC RST/NMI PIN Test PINVCC Bootstrap loader StartsTest InternalFlash memory control register FCTL1 Flash memoryErase 0128h, bit1, Erase a segment Flash memory, timing generator, control register FCTL2WRT FN0±FN5 Flash memory control register FCTL3SSEL0, SSEL1 AclkKeyv BusyAccvifg WaitLock Flash memory, interrupt and security key violationEmex PUC AccvPOR NmirsOscillator and system clock PeripheralsDigital I/O Clock SignalsTimerA Three capture/compare registers Watchdog timerTimerA, MSP430x11x1 Configuration TimerA 3 capture/compare registersComparatorA CAF CaoutCACTL2.4 CATCTL2.7CACTL1 Slope a/d conversionCaex Caon Caies Caifg Rsel REF1 REF0 CACTL2Peripherals with Byte Access Peripherals with Word AccessPeripheral file map Recommended operating conditions Absolute maximum ratings²MIN NOM MAX Units Frequency vs Supply Voltage MSP430x11x1 DevicesIAM Parameter Test Conditions MIN TYP MAX UnitILPM2 ILPM3Leakage current Outputs Port 1 to P2 P1.0 to P1.7, P2.0 to P2.5Inputs Px.x, TAx Internal signals TAx, Smclk at TimerAParameter Test Conditions VCC MIN TYP MAX Unit Port P1, P2 P1.x to P2.xComparatorA see Note Outputs P1.x, P2.x, TAxVRefVT vs Temperature, VCC = 2.2 V, C1121 VRefVT vs Temperature, VCC = 3 V, C1121CAF Caon PUC/PORParameter MIN NOM MAX Unit RAMVariance Max DCODcoclk DCO StepsWake-up from lower power modes LPMx Principle characteristics of the DCOJTAG/programming Port P1, P1.0 to P1.3, input/output with Schmitt-trigger Input/output schematicGND P1IFG.4 P1IES.4 P1DIR.4 P1OUT.4 SmclkP1DIR.5 P1OUT.5 P1IFG.5 P1IES.5CAPD.X Port P2, P2.0 to P2.2, input/output with Schmitt-triggerP2DIR.3 P2OUT.3 Port P2, P2.3 to P2.4, input/output with Schmitt-triggerP2IFG.3 P1IES.3 P2DIR.4 P2OUT.4P2DIR.5 P2SEL.5 VCCP2OUT.5 P2IRQ.5Port P2, unbonded bits P2.6 and P2.7 DW R-PDSO-G Pins DIM MAXPlastic SMALL-OUTLINE Package PIN ShownPins DIM MAX MIN Pins ShownPW R-PDSO-G Plastic SMALL-OUTLINE Package 15 NOM Gage Plane Seating Plane 20 MAXImportant Notice