Texas Instruments MSP430x11x1 warranty Puc/Por, CAF Caon

Page 33

MSP430x11x1

MIXED SIGNAL MICROCONTROLLER

SLAS241C ± SEPTEMBER 1999 ± REVISED JUNE 2000

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued)

 

0 V

VCC

 

 

 

0

1

CAF

 

 

 

CAON

 

 

 

 

 

 

 

 

Low Pass Filter

To Internal

 

 

 

 

Modules

V+ +

0

0

 

 

 

 

V±

_

1

1

 

 

 

 

 

 

 

CAOUT

 

 

 

 

Set CAIFG

 

 

 

 

Flag

 

 

 

τ ≈ 2.0 ∝s

 

Figure 9. Block Diagram of Comparator_A Module

Overdrive

VCAOUT

V±

 

400 mV

 

V+

t(response)

Figure 10. Overdrive Definition

PUC/POR

 

PARAMETER

TEST CONDITIONS

MIN TYP

MAX

UNIT

 

 

 

 

 

 

 

t(POR_delay)

 

 

 

150

250

∝s

 

 

TA = ±40°C

 

1.4

1.8

V

V(POR)

POR

TA = 25°C

VCC = 2.2 V/3 V

1.1

1.5

V

 

 

TA = 85°C

0.8

1.2

V

 

 

 

V(min)

 

 

 

0

0.4

V

t(reset)

PUC/POR

Reset is accepted internally

 

2

 

∝s

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

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Contents MSP430x11x1 DescriptionTssop Available Options Packaged Devices Functional block diagramPIN Sowb PIN Tssop Pulldown resistor of 30 k Ω is needed on F11x1Short-form description Terminal FunctionsProcessing unit Terminal Description NameCPU Address Mode DescriptionsInstruction set Instruction Word FormatsOperation modes and interrupts Low-power consumption capabilitiesSCG1 Status register R2SCG0 SCG1 SCG0Caifg Interrupt vector addressesWdtifg CCIFG1, CCIFG2, TaifgWdtifg Special function registersOfifg NmiifgBoot ROM containing bootstrap loader Functions of the bootstrap loaderMemory organization Hardware resources used for serial input/output Features of the bootstrap loader areWDT VCC RST/NMI PIN Test PINVCC Bootstrap loader StartsTest InternalFlash memory control register FCTL1 Flash memoryFlash memory, timing generator, control register FCTL2 Erase 0128h, bit1, Erase a segmentWRT FN0±FN5 Flash memory control register FCTL3SSEL0, SSEL1 AclkKeyv BusyAccvifg WaitFlash memory, interrupt and security key violation LockEmex PUC AccvPOR NmirsOscillator and system clock PeripheralsDigital I/O Clock SignalsTimerA Three capture/compare registers Watchdog timerTimerA, MSP430x11x1 Configuration TimerA 3 capture/compare registersComparatorA CAF CaoutCACTL2.4 CATCTL2.7CACTL1 Slope a/d conversionCaex Caon Caies Caifg Rsel REF1 REF0 CACTL2Peripherals with Word Access Peripherals with Byte AccessPeripheral file map Absolute maximum ratings² Recommended operating conditionsMIN NOM MAX Units Frequency vs Supply Voltage MSP430x11x1 DevicesIAM Parameter Test Conditions MIN TYP MAX UnitILPM2 ILPM3Leakage current Outputs Port 1 to P2 P1.0 to P1.7, P2.0 to P2.5Inputs Px.x, TAx Internal signals TAx, Smclk at TimerAParameter Test Conditions VCC MIN TYP MAX Unit Port P1, P2 P1.x to P2.xComparatorA see Note Outputs P1.x, P2.x, TAxVRefVT vs Temperature, VCC = 2.2 V, C1121 VRefVT vs Temperature, VCC = 3 V, C1121CAF Caon PUC/PORParameter MIN NOM MAX Unit RAMVariance Max DCODcoclk DCO StepsPrinciple characteristics of the DCO Wake-up from lower power modes LPMxJTAG/programming Input/output schematic Port P1, P1.0 to P1.3, input/output with Schmitt-triggerGND P1IFG.4 P1IES.4 P1DIR.4 P1OUT.4 SmclkP1DIR.5 P1OUT.5 P1IFG.5 P1IES.5CAPD.X Port P2, P2.0 to P2.2, input/output with Schmitt-triggerP2DIR.3 P2OUT.3 Port P2, P2.3 to P2.4, input/output with Schmitt-triggerP2IFG.3 P1IES.3 P2DIR.4 P2OUT.4P2DIR.5 P2SEL.5 VCCP2OUT.5 P2IRQ.5Port P2, unbonded bits P2.6 and P2.7 DW R-PDSO-G Pins DIM MAXPlastic SMALL-OUTLINE Package PIN ShownPins DIM MAX MIN Pins ShownPW R-PDSO-G Plastic SMALL-OUTLINE Package 15 NOM Gage Plane Seating Plane 20 MAXImportant Notice
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