Texas Instruments MSP430x11x1 warranty Clock Signals, Digital I/O

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MSP430x11x1

MIXED SIGNAL MICROCONTROLLER

SLAS241C ± SEPTEMBER 1999 ± REVISED JUNE 2000

oscillator and system clock (continued)

 

DIVA

 

 

2

 

LFXT1CLK

 

ACLK

 

/1, /2, /4, /8

OSCOff XTS

 

Auxiliary Clock

 

 

XIN

ACLKGEN

 

SELM

DIVM CPUOff

 

LFXT1 OSCILLATOR

 

 

2

2

 

3

 

 

0,1

/1, /2, /4, /8, Off

MCLK

XOUT

2

 

Main System Clock

DCOCLK

MCLKGEN

 

 

 

VCCVCC

Rsel SCG0

DCO

MOD

 

 

 

3

 

5

 

 

SELS

DIVS

SCG1

 

 

 

 

 

 

 

 

2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

Digital Controlled Oscillator (DCO)

0

 

 

DC

 

 

+

/1, /2, /4, /8, Off

SMCLK

 

Generator

 

Modulator (MOD)

 

Subsystem Clock

 

1

1

 

 

P2.5/Rosc

 

 

 

 

 

DCGEN

DCOMOD

SMCLKGEN

 

 

 

 

DCOR

 

 

 

 

 

The DCO-Generator is connected to pin P2.5/Rosc if DCOR control bit is set.

 

 

 

The port pin P2.5/Rosc is selected if DCOR control bit is reset (initial state).

 

P2.5

Figure 3. Clock Signals

Two clock sources, LFXT1CLK and DCOCLK, can be used to drive the MSP430 system. The LFXT1CLK is generated from the LFXT1 crystal oscillator. The LFXT1 crystal oscillator can operate in three modesÐlow frequency (LF), moderate frequency (XT1), and external input mode. The LFXT1 crystal oscillator may be switched off when it is not in use.

DCOCLK is generated from the DCO. The nominal DCO frequency is defined by the dc generator and can be set by one external resistor, or can be set to one of eight values with integrated resistors. Additional adjustments and modulations of DCOCLK are possible by software manipulation of registers in the DCO module. DCOCLK is stopped automatically when it is not used by the CPU or peripheral modules. The dc generator can be shut down with the SCG0 bit to realize additional power savings when DCOCLK is not in use.

NOTE:

The system clock generator always starts with the DCOCLK selected for MCLK (CPU clock) to ensure proper start of program execution. The software defines the final system clock generation through control bit manipulation.

digital I/O

There are two eight-bit I/O ports, port P1 and port P2 ± implemented (11x1 parts only have six port P2 I/O signals available on external pins). Both ports, P1 and P2, have seven control registers to give maximum flexibility of digital input/output to the application:

All individual I/O bits are programmable independently.

Any combination of input, output, and interrupt conditions is possible.

Interrupt processing of external events is fully implemented for all eight bits of port P1 and for six bits of port P2.

Read/write access to all registers with all instructions

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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Contents Description MSP430x11x1Tssop Pulldown resistor of 30 k Ω is needed on F11x1 Functional block diagramAvailable Options Packaged Devices PIN Sowb PIN TssopTerminal Description Name Terminal FunctionsShort-form description Processing unitInstruction Word Formats Address Mode DescriptionsCPU Instruction setOperation modes and interrupts Low-power consumption capabilitiesSCG1 SCG0 Status register R2SCG1 SCG0CCIFG1, CCIFG2, Taifg Interrupt vector addressesCaifg WdtifgNmiifg Special function registersWdtifg OfifgFunctions of the bootstrap loader Boot ROM containing bootstrap loaderMemory organization VCC RST/NMI PIN Test PIN Features of the bootstrap loader areHardware resources used for serial input/output WDTInternal Bootstrap loader StartsVCC TestFlash memory control register FCTL1 Flash memoryErase 0128h, bit1, Erase a segment Flash memory, timing generator, control register FCTL2WRT Aclk Flash memory control register FCTL3FN0±FN5 SSEL0, SSEL1Wait BusyKeyv AccvifgLock Flash memory, interrupt and security key violationEmex Nmirs AccvPUC POROscillator and system clock PeripheralsDigital I/O Clock SignalsTimerA Three capture/compare registers Watchdog timerTimerA, MSP430x11x1 Configuration TimerA 3 capture/compare registersComparatorA CATCTL2.7 CaoutCAF CACTL2.4CACTL2 Slope a/d conversionCACTL1 Caex Caon Caies Caifg Rsel REF1 REF0Peripherals with Byte Access Peripherals with Word AccessPeripheral file map Recommended operating conditions Absolute maximum ratings²MIN NOM MAX Units Frequency vs Supply Voltage MSP430x11x1 DevicesILPM3 Parameter Test Conditions MIN TYP MAX UnitIAM ILPM2Leakage current Outputs Port 1 to P2 P1.0 to P1.7, P2.0 to P2.5Port P1, P2 P1.x to P2.x Internal signals TAx, Smclk at TimerAInputs Px.x, TAx Parameter Test Conditions VCC MIN TYP MAX UnitComparatorA see Note Outputs P1.x, P2.x, TAxVRefVT vs Temperature, VCC = 2.2 V, C1121 VRefVT vs Temperature, VCC = 3 V, C1121CAF Caon PUC/PORParameter MIN NOM MAX Unit RAMDCO Steps DCOVariance Max DcoclkWake-up from lower power modes LPMx Principle characteristics of the DCOJTAG/programming Port P1, P1.0 to P1.3, input/output with Schmitt-trigger Input/output schematicGND P1IFG.5 P1IES.5 P1DIR.4 P1OUT.4 SmclkP1IFG.4 P1IES.4 P1DIR.5 P1OUT.5CAPD.X Port P2, P2.0 to P2.2, input/output with Schmitt-triggerP2DIR.4 P2OUT.4 Port P2, P2.3 to P2.4, input/output with Schmitt-triggerP2DIR.3 P2OUT.3 P2IFG.3 P1IES.3P2IRQ.5 P2SEL.5 VCCP2DIR.5 P2OUT.5Port P2, unbonded bits P2.6 and P2.7 PIN Shown Pins DIM MAXDW R-PDSO-G Plastic SMALL-OUTLINE Package15 NOM Gage Plane Seating Plane 20 MAX Pins ShownPins DIM MAX MIN PW R-PDSO-G Plastic SMALL-OUTLINE PackageImportant Notice