Texas Instruments Managing EMEX and BUSY States in Mixed Signal Microcontrollers

MSP430x11x1

MIXED SIGNAL MICROCONTROLLER

SLAS241C ± SEPTEMBER 1999 ± REVISED JUNE 2000

flash memory, timing generator, control register FCTL2 (continued)

The flash timing generator is reset with PUC. It is also reset if the emergency exit bit EMEX is set.

Control register FCTL2 may not be written to if the BUSY bit is set; otherwise, an access violation will occur (ACCVIFG=1).

Read access is possible at any time without restrictions.

SSEL1	SSEL0
	0	FN5.......... FN0
ACLK
MCLK	1	Divider,	fX
SMCLK	2	1 .. 64
SMCLK	3

Write '1' to

PUC EMEX

Reset

Flash Timing

Generator

BUSY WAIT

Figure 1. Flash Memory Timing Generator Diagram

15

FCTL2

012Ah

FCTL2 read:

FCTL2 write:

8	7							0
	SSEL1	SSEL0	FN5	FN4	FN3	FN2	FN1		FN0
	rw±0	rw±1	rw-0	rw-0	rw-0	rw±0	rw-1		rw-0

096h

0A5h

The control bits are:
FN0±FN5	012Ah, bit0±5	These six bits define the division rate of the clock signal. The division
		rate is 1 to 64, according to the digital value of FN5 to FN0 plus one.
SSEL0, SSEL1	012Ah, bit6,7	Clock source select
		0: ACLK

1: MCLK

2: SMCLK

3: SMCLK

The flash timing generator is reset with PUC. It is also reset if the EMEX bit is set.

flash memory control register FCTL3

There are no restrictions to modify this control register.

15

FCTL3

012Ch

8	7							0
	res.	res.	EMEX	Lock	WAIT	ACCV	KEYV	BUSY
						IFG
	r0	r0	rw-0	rw-1	rw-1	rw±0 rw-(0)		r(w)-0

FCTL3 read:	096h
FCTL3 write:
	0A5h

14 POST OFFICE BOX 655303 •DALLAS, TEXAS 75265