Texas Instruments MSP430x11x1 Slope a/d conversion, CACTL1, Caex Caon Caies Caifg Rsel REF1 REF0

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MSP430x11x1

MIXED SIGNAL MICROCONTROLLER

SLAS241C ± SEPTEMBER 1999 ± REVISED JUNE 2000

Comparator_A (continued)

CACTL1

059h

	7							0

	CAEX	CA	CA	CA	CAON	CAIES	CAIE	CAIFG
	CAEX	RSEL	REF1	REF0	CAON	CAIES	CAIE	CAIFG
		RSEL	REF1	REF0

	rw-(0)	rw-(0)	rw-(0)	rw-(0) rw-(0)		rw-(0)	rw-(0)	rw-(0)

CACTL2

05Ah

CAPD 05Bh

	7							0
	CACTL	CACTL	CACTL	CACTL	CA1	CA0	CAF	CAOUT
	2.7	2.6	2.5	2.4	CA1	CA0	CAF	CAOUT
	2.7	2.6	2.5	2.4

	rw-(0)	rw-(0)	rw-(0)	rw-(0)	rw-(0)	rw-(0)	rw-(0)	r-(0)
	7							0

	CAPD7	CAPD6	CAPD5	CAPD4	CAPD3	CAPD2	CAPD1	CAPD0

	rw-(0)	rw-(0)	rw-(0)	rw-(0)	rw-(0)	rw-(0)	rw-(0)	rw-(0)

NOTE:

Ensure that the comparator input terminals are connected to signal, power, or ground level. Otherwise, floating levels may cause unexpected interrupts and current consumption may be increased.

slope a/d conversion

The Comparator_A is well suited for use in single or multiple-slope conversions. The internal-reference levels may be used to set a reference during timing measurement of charge or discharge operations. They can also be used externally to bias analog circuitry.

Voltage, current, and resistive or capacitive sensor measurements are basic functions. The sensors sense physical conditions like temperature, pressure, acceleration, etc.

24	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

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Contents MSP430x11x1 DescriptionTssop Functional block diagram Available Options Packaged DevicesPIN Sowb PIN Tssop Pulldown resistor of 30 k Ω is needed on F11x1Terminal Functions Short-form descriptionProcessing unit Terminal Description NameAddress Mode Descriptions CPUInstruction set Instruction Word FormatsLow-power consumption capabilities Operation modes and interruptsStatus register R2 SCG1SCG0 SCG1 SCG0Interrupt vector addresses CaifgWdtifg CCIFG1, CCIFG2, TaifgSpecial function registers WdtifgOfifg NmiifgBoot ROM containing bootstrap loader Functions of the bootstrap loaderMemory organization Features of the bootstrap loader are Hardware resources used for serial input/outputWDT VCC RST/NMI PIN Test PINBootstrap loader Starts VCCTest InternalFlash memory Flash memory control register FCTL1Flash memory, timing generator, control register FCTL2 Erase 0128h, bit1, Erase a segmentWRT Flash memory control register FCTL3 FN0±FN5SSEL0, SSEL1 AclkBusy KeyvAccvifg WaitFlash memory, interrupt and security key violation LockEmex Accv PUCPOR NmirsPeripherals Oscillator and system clockClock Signals Digital I/OWatchdog timer TimerA Three capture/compare registersTimerA 3 capture/compare registers TimerA, MSP430x11x1 ConfigurationComparatorA Caout CAFCACTL2.4 CATCTL2.7Slope a/d conversion CACTL1Caex Caon Caies Caifg Rsel REF1 REF0 CACTL2Peripherals with Word Access Peripherals with Byte AccessPeripheral file map Absolute maximum ratings² Recommended operating conditionsMIN NOM MAX Units MSP430x11x1 Devices Frequency vs Supply VoltageParameter Test Conditions MIN TYP MAX Unit IAMILPM2 ILPM3Outputs Port 1 to P2 P1.0 to P1.7, P2.0 to P2.5 Leakage currentInternal signals TAx, Smclk at TimerA Inputs Px.x, TAxParameter Test Conditions VCC MIN TYP MAX Unit Port P1, P2 P1.x to P2.xOutputs P1.x, P2.x, TAx ComparatorA see NoteVRefVT vs Temperature, VCC = 3 V, C1121 VRefVT vs Temperature, VCC = 2.2 V, C1121PUC/POR CAF CaonRAM Parameter MIN NOM MAX UnitDCO Variance MaxDcoclk DCO StepsPrinciple characteristics of the DCO Wake-up from lower power modes LPMxJTAG/programming Input/output schematic Port P1, P1.0 to P1.3, input/output with Schmitt-triggerGND P1DIR.4 P1OUT.4 Smclk P1IFG.4 P1IES.4P1DIR.5 P1OUT.5 P1IFG.5 P1IES.5Port P2, P2.0 to P2.2, input/output with Schmitt-trigger CAPD.XPort P2, P2.3 to P2.4, input/output with Schmitt-trigger P2DIR.3 P2OUT.3P2IFG.3 P1IES.3 P2DIR.4 P2OUT.4P2SEL.5 VCC P2DIR.5P2OUT.5 P2IRQ.5Port P2, unbonded bits P2.6 and P2.7 Pins DIM MAX DW R-PDSO-GPlastic SMALL-OUTLINE Package PIN ShownPins Shown Pins DIM MAX MINPW R-PDSO-G Plastic SMALL-OUTLINE Package 15 NOM Gage Plane Seating Plane 20 MAXImportant Notice