Texas Instruments MSP430x11x1 warranty Outputs P1.x, P2.x, TAx, ComparatorA see Note

Page 31

MSP430x11x1

MIXED SIGNAL MICROCONTROLLER

SLAS241C ± SEPTEMBER 1999 ± REVISED JUNE 2000

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued)

outputs P1.x, P2.x, TAx

PARAMETER

 

TEST CONDITIONS

VCC

MIN

TYP

MAX

UNIT

 

 

 

 

 

 

 

 

 

 

 

f(P20)

 

P2.0/ACLK,

 

CL = 20 pF

 

2.2 V/3 V

 

 

fSystem

 

f(TAx)

Output frequency

TA0, TA1, TA2,

 

CL = 20 pF

 

2.2 V/3 V

dc

 

fSystem

MHz

 

Internal clock source, SMCLK signal applied (see Note 16)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

fSMCLK = fLFXT1 = fXT1

 

40%

 

60%

 

 

 

P1.4/SMCLK,

 

fSMCLK = fLFXT1 = fLF

2.2 V/3 V

35%

 

65%

 

 

 

 

 

 

 

 

50%±

 

50%+

 

 

 

CL = 20 pF

 

f

SMCLK

= f

LFXT1/n

 

50%

 

 

 

 

 

15 ns

15 ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

t(Xdc)

Duty cycle of O/P

 

 

fSMCLK = fDCOCLK

2.2 V/3 V

50%±

50%

50%+

 

 

frequency

 

 

15 ns

15 ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P2.0/ACLK,

 

fP20 = fLFXT1 = fXT1

 

40%

 

60%

 

 

 

 

fP20 = fLFXT1 = fLF

2.2 V/3 V

30%

 

70%

 

 

 

CL = 20 pF

 

 

 

 

 

 

fP20 = fLFXT1/n

 

 

50%

 

 

 

 

 

 

 

 

 

 

t(TAdc)

 

TA0, TA1, TA2,

 

CL = 20 pF,

Duty cycle = 50%

2.2 V/3 V

 

0

±50

ns

NOTE 16: The limits of the system clock MCLK has to be met. MCLK and SMCLK can have different frequencies.

 

 

 

Comparator_A (see Note 17)

 

PARAMETER

 

 

 

 

TEST CONDITIONS

 

 

 

MIN

TYP

MAX

UNIT

 

 

 

 

 

 

 

 

 

 

 

 

 

I(DD)

 

 

 

 

 

CAON=1,

CARSEL=0, CAREF=0

VCC = 2.2 V

 

25

40

∝A

 

 

 

 

 

VCC = 3 V

 

45

60

 

 

 

 

 

 

 

 

 

 

I(Refladder/

 

 

 

 

 

CAON=1,

CARSEL=0,

VCC = 2.2 V

 

30

50

 

 

 

 

 

 

CAREF=1/2/3, No load at

 

∝A

RefDiode)

 

 

 

 

 

VCC = 3 V

 

45

71

 

 

 

 

 

P2.3/CA0/TA1 and P2.4/CA1/TA2

 

 

V(IC)

 

Common-mode input

 

 

 

CAON =1

 

VCC = 2.2 V/3 V

0

 

VCC±1

V

 

voltage

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

V(Ref025)

Voltage @ 0.25 VCC

node

PCA0=1,

CARSEL=1, CAREF=1,

 

 

 

 

 

 

 

No load at P2.3/CA0/TA1 and

VCC = 2.2 V/3 V

0.23

0.24

0.25

 

See Figure 5

 

VCC

 

 

 

 

 

 

 

 

P2.4/CA1/TA2, See Figure 5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

V(Ref050)

Voltage @ 0.5 VCC node

PCA0=1,

CARSEL=1, CAREF=2,

 

 

 

 

 

 

 

No load at P2.3/CA0/TA1 and

VCC = 2.2 V/3 V

0.47

0.48

0.5

 

See Figure 5

 

VCC

 

 

 

 

 

 

 

 

P2.4/CA1/TA2, See Figure 5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCA0=1,

CARSEL=1, CAREF=3,

VCC = 2.2 V

430

550

645

 

V(RefVT)

 

 

 

 

 

No load at P2.3/CA0/TA1 and

 

 

 

 

 

 

mV

 

 

 

 

 

VCC = 3 V

450

565

660

 

 

 

 

 

 

P2.4/CA1/TA2

 

V(offset)

 

Offset voltage

 

 

 

See Note 18

VCC = 2.2 V/3 V

±30

 

30

mV

Vhys

 

Input hysteresis

 

 

 

CAON=1

 

VCC = 2.2 V/3 V

0

0.7

1.4

mV

 

 

 

 

 

 

°

 

V

CC

= 2.2 V

160

210

300

 

 

 

 

 

 

 

TA = 25 C, Overdrive 10 mV, With-

 

 

 

 

 

ns

 

 

 

 

 

 

out filter:

CAF=0

VCC = 3 V

90

150

200

 

 

 

 

 

 

 

t(response LH)

 

 

 

 

 

 

 

 

 

 

 

 

 

°

 

V

CC

= 2.2 V

1.6

1.9

3.4

 

 

 

 

 

 

 

TA = 25 C, Overdrive 10 mV, With

 

 

 

 

 

∝s

 

 

 

 

 

 

filter: CAF=1

VCC = 3 V

1.1

1.5

2.6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TA = 25°C,

 

V

CC

= 2.2 V

160

210

300

 

 

 

 

 

 

 

Overdrive 10 mV, without filter:

 

 

 

 

 

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VCC = 3 V

90

150

200

t(response HL)

 

 

 

 

 

CAF=0

 

 

 

 

 

 

 

 

°

 

V

CC

= 2.2 V

1.6

1.9

3.4

 

 

 

 

 

 

 

TA = 25 C,

 

 

 

 

 

 

∝s

 

 

 

 

 

 

Overdrive 10 mV, with filter: CAF=1

VCC = 3 V

1.1

1.5

2.6

 

 

 

 

 

 

 

NOTES: 17. The leakage current for the Comparator_A terminals is identical to Ilkg(Px.x) specification.

18.The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A inputs on successive measurements. The two successive measurements are then summed together.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

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Contents Description MSP430x11x1Tssop Pulldown resistor of 30 k Ω is needed on F11x1 Functional block diagramAvailable Options Packaged Devices PIN Sowb PIN TssopTerminal Description Name Terminal FunctionsShort-form description Processing unitInstruction Word Formats Address Mode DescriptionsCPU Instruction setOperation modes and interrupts Low-power consumption capabilitiesSCG1 SCG0 Status register R2SCG1 SCG0CCIFG1, CCIFG2, Taifg Interrupt vector addressesCaifg WdtifgNmiifg Special function registersWdtifg OfifgFunctions of the bootstrap loader Boot ROM containing bootstrap loaderMemory organization VCC RST/NMI PIN Test PIN Features of the bootstrap loader areHardware resources used for serial input/output WDTInternal Bootstrap loader StartsVCC TestFlash memory control register FCTL1 Flash memoryErase 0128h, bit1, Erase a segment Flash memory, timing generator, control register FCTL2WRT Aclk Flash memory control register FCTL3FN0±FN5 SSEL0, SSEL1Wait BusyKeyv AccvifgLock Flash memory, interrupt and security key violationEmex Nmirs AccvPUC POROscillator and system clock PeripheralsDigital I/O Clock SignalsTimerA Three capture/compare registers Watchdog timerTimerA, MSP430x11x1 Configuration TimerA 3 capture/compare registersComparatorA CATCTL2.7 CaoutCAF CACTL2.4CACTL2 Slope a/d conversionCACTL1 Caex Caon Caies Caifg Rsel REF1 REF0Peripherals with Byte Access Peripherals with Word AccessPeripheral file map Recommended operating conditions Absolute maximum ratings²MIN NOM MAX Units Frequency vs Supply Voltage MSP430x11x1 DevicesILPM3 Parameter Test Conditions MIN TYP MAX UnitIAM ILPM2Leakage current Outputs Port 1 to P2 P1.0 to P1.7, P2.0 to P2.5Port P1, P2 P1.x to P2.x Internal signals TAx, Smclk at TimerAInputs Px.x, TAx Parameter Test Conditions VCC MIN TYP MAX UnitComparatorA see Note Outputs P1.x, P2.x, TAxVRefVT vs Temperature, VCC = 2.2 V, C1121 VRefVT vs Temperature, VCC = 3 V, C1121CAF Caon PUC/PORParameter MIN NOM MAX Unit RAMDCO Steps DCOVariance Max DcoclkWake-up from lower power modes LPMx Principle characteristics of the DCOJTAG/programming Port P1, P1.0 to P1.3, input/output with Schmitt-trigger Input/output schematicGND P1IFG.5 P1IES.5 P1DIR.4 P1OUT.4 SmclkP1IFG.4 P1IES.4 P1DIR.5 P1OUT.5CAPD.X Port P2, P2.0 to P2.2, input/output with Schmitt-triggerP2DIR.4 P2OUT.4 Port P2, P2.3 to P2.4, input/output with Schmitt-triggerP2DIR.3 P2OUT.3 P2IFG.3 P1IES.3P2IRQ.5 P2SEL.5 VCCP2DIR.5 P2OUT.5Port P2, unbonded bits P2.6 and P2.7 PIN Shown Pins DIM MAXDW R-PDSO-G Plastic SMALL-OUTLINE Package15 NOM Gage Plane Seating Plane 20 MAX Pins ShownPins DIM MAX MIN PW R-PDSO-G Plastic SMALL-OUTLINE PackageImportant Notice
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