Texas Instruments MSP430x11x1 Port P2, P2.0 to P2.2, input/output with Schmitt-trigger, Capd.X

Page 39

 

 

 

MSP430x11x1

 

 

 

MIXED SIGNAL MICROCONTROLLER

 

 

 

SLAS241C ± SEPTEMBER 1999 ± REVISED JUNE 2000

 

APPLICATION INFORMATION

Port P2, P2.0 to P2.2, input/output with Schmitt-trigger

 

P2SEL.x

0

 

VCC

P2DIR.x

0: Input

 

 

See Note 27

Direction Control

1

1: Output

 

From Module

 

 

 

 

 

 

0

Pad Logic

See Note 28

P2OUT.x

P2.0 ± P2.2

 

 

Module X OUT

1

 

 

 

 

 

 

 

 

See Note 28

 

 

 

See Note 27

 

 

 

GND

 

 

 

Bus Keeper

P2IN.x

 

 

EN

Module X IN

D

CAPD.X

 

 

P2IRQ.x

P2IE.x

EN

 

 

 

Interrupt

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Q

 

 

Edge

 

 

 

 

 

 

 

 

 

 

P2IFG.x

 

 

 

 

 

 

 

 

 

 

Set

 

 

Select

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Interrupt

 

 

 

 

 

 

 

 

 

NOTE: x = Bit Identifier, 0 to 2 for port P2

 

Flag

P2IES.x

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P2SEL.x

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Direction

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PnSel.x

PnDIR.x

 

control from

 

PnOUT.x

Module X OUT

 

PnIN.x

 

Module X IN

PnIE.x

PnIFG.x

PnIES.x

 

 

 

module

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P2Sel.0

P2DIR.0

 

P2DIR.0

 

P2OUT.0

ACLK

 

P2IN.0

 

unused

P2IE.0

P2IFG.0

P1IES.0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P2Sel.1

P2DIR.1

 

P2DIR.1

 

P2OUT.1

VSS

 

P2IN.1

 

INCLK²

P2IE.1

P2IFG.1

P1IES.1

P2Sel.2

P2DIR.2

 

P2DIR.2

 

 

P2OUT.2

CAOUT

 

P2IN.2

 

CCI0B²

P2IE.2

P2IFG.2

P1IES.2

² Signal from or to Timer_A

NOTES: 27. Optional selection of pullup or pulldown resistors with ROM (masked) versions.

28. Fuses for optional pullup and pulldown resistors can only be programmed at the factory (ROM versions only).

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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Contents MSP430x11x1 DescriptionTssop Pulldown resistor of 30 k Ω is needed on F11x1 Functional block diagramAvailable Options Packaged Devices PIN Sowb PIN TssopTerminal Description Name Terminal FunctionsShort-form description Processing unitInstruction Word Formats Address Mode DescriptionsCPU Instruction setOperation modes and interrupts Low-power consumption capabilitiesSCG1 SCG0 Status register R2SCG1 SCG0CCIFG1, CCIFG2, Taifg Interrupt vector addressesCaifg WdtifgNmiifg Special function registersWdtifg OfifgBoot ROM containing bootstrap loader Functions of the bootstrap loaderMemory organization VCC RST/NMI PIN Test PIN Features of the bootstrap loader areHardware resources used for serial input/output WDTInternal Bootstrap loader StartsVCC TestFlash memory control register FCTL1 Flash memoryFlash memory, timing generator, control register FCTL2 Erase 0128h, bit1, Erase a segmentWRT Aclk Flash memory control register FCTL3FN0±FN5 SSEL0, SSEL1Wait BusyKeyv AccvifgFlash memory, interrupt and security key violation LockEmex Nmirs AccvPUC POROscillator and system clock PeripheralsDigital I/O Clock SignalsTimerA Three capture/compare registers Watchdog timerTimerA, MSP430x11x1 Configuration TimerA 3 capture/compare registersComparatorA CATCTL2.7 CaoutCAF CACTL2.4CACTL2 Slope a/d conversionCACTL1 Caex Caon Caies Caifg Rsel REF1 REF0Peripherals with Word Access Peripherals with Byte AccessPeripheral file map Absolute maximum ratings² Recommended operating conditionsMIN NOM MAX Units Frequency vs Supply Voltage MSP430x11x1 DevicesILPM3 Parameter Test Conditions MIN TYP MAX UnitIAM ILPM2Leakage current Outputs Port 1 to P2 P1.0 to P1.7, P2.0 to P2.5Port P1, P2 P1.x to P2.x Internal signals TAx, Smclk at TimerAInputs Px.x, TAx Parameter Test Conditions VCC MIN TYP MAX UnitComparatorA see Note Outputs P1.x, P2.x, TAxVRefVT vs Temperature, VCC = 2.2 V, C1121 VRefVT vs Temperature, VCC = 3 V, C1121CAF Caon PUC/PORParameter MIN NOM MAX Unit RAMDCO Steps DCOVariance Max DcoclkPrinciple characteristics of the DCO Wake-up from lower power modes LPMxJTAG/programming Input/output schematic Port P1, P1.0 to P1.3, input/output with Schmitt-triggerGND P1IFG.5 P1IES.5 P1DIR.4 P1OUT.4 SmclkP1IFG.4 P1IES.4 P1DIR.5 P1OUT.5CAPD.X Port P2, P2.0 to P2.2, input/output with Schmitt-triggerP2DIR.4 P2OUT.4 Port P2, P2.3 to P2.4, input/output with Schmitt-triggerP2DIR.3 P2OUT.3 P2IFG.3 P1IES.3P2IRQ.5 P2SEL.5 VCCP2DIR.5 P2OUT.5Port P2, unbonded bits P2.6 and P2.7 PIN Shown Pins DIM MAXDW R-PDSO-G Plastic SMALL-OUTLINE Package15 NOM Gage Plane Seating Plane 20 MAX Pins ShownPins DIM MAX MIN PW R-PDSO-G Plastic SMALL-OUTLINE PackageImportant Notice