Texas Instruments MSP430x11x1 warranty ComparatorA

Page 22

MSP430x11x1

MIXED SIGNAL MICROCONTROLLER

SLAS241C ± SEPTEMBER 1999 ± REVISED JUNE 2000

Comparator_A

The primary function of the comparator module is to support precision A/D slope conversion applications, battery voltage supervision, and observation of external analog signals. The comparator is connected to port pins P2.3/CA0 and to P2.4/CA1. It is controlled via twelve control bits in registers CACTL1 and CACTL2.

P2CA0

0	CA0

P2.3/ 1

CA0/

TA1

0 CA1

P2.4/ 1

CA1/

TA2

P2CA1

CARSEL

0 VCAREF

	0 V	VCC
	0	1			CAF
	CAEX	CAON
		CAON
0					Low Pass Filter
					Low Pass Filter
1				0	0
	+			0	0
	+
0	_			1	1
				1	1

1	0 V
			0 V	VCC	0 V
			0	1	τ ≈ 2.0 ∝s
					τ ≈ 2.0 ∝s
				CAON
		3	2	1	0
					CAREF

0	0.5 x VCC
	0.5 x VCC
2
1	0.25 x VCC
	0.25 x VCC
3

CCI1B

CAOUT

Set CAIFG

Flag

P2.2/

CAOUT/TA0

0 V

Figure 5. Block Diagram of Comparator_A

22	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

Image 22

Contents Description MSP430x11x1Tssop PIN Sowb PIN Tssop Functional block diagramAvailable Options Packaged Devices Pulldown resistor of 30 k Ω is needed on F11x1Processing unit Terminal FunctionsShort-form description Terminal Description NameInstruction set Address Mode DescriptionsCPU Instruction Word FormatsLow-power consumption capabilities Operation modes and interruptsSCG0 Status register R2SCG1 SCG1 SCG0Wdtifg Interrupt vector addressesCaifg CCIFG1, CCIFG2, TaifgOfifg Special function registersWdtifg NmiifgFunctions of the bootstrap loader Boot ROM containing bootstrap loaderMemory organization WDT Features of the bootstrap loader areHardware resources used for serial input/output VCC RST/NMI PIN Test PINTest Bootstrap loader StartsVCC InternalFlash memory Flash memory control register FCTL1Erase 0128h, bit1, Erase a segment Flash memory, timing generator, control register FCTL2WRT SSEL0, SSEL1 Flash memory control register FCTL3FN0±FN5 AclkAccvifg BusyKeyv WaitLock Flash memory, interrupt and security key violationEmex POR AccvPUC NmirsPeripherals Oscillator and system clockClock Signals Digital I/OWatchdog timer TimerA Three capture/compare registersTimerA 3 capture/compare registers TimerA, MSP430x11x1 ConfigurationComparatorA CACTL2.4 CaoutCAF CATCTL2.7Caex Caon Caies Caifg Rsel REF1 REF0 Slope a/d conversionCACTL1 CACTL2Peripherals with Byte Access Peripherals with Word AccessPeripheral file map Recommended operating conditions Absolute maximum ratings²MIN NOM MAX Units MSP430x11x1 Devices Frequency vs Supply VoltageILPM2 Parameter Test Conditions MIN TYP MAX UnitIAM ILPM3Outputs Port 1 to P2 P1.0 to P1.7, P2.0 to P2.5 Leakage currentParameter Test Conditions VCC MIN TYP MAX Unit Internal signals TAx, Smclk at TimerAInputs Px.x, TAx Port P1, P2 P1.x to P2.xOutputs P1.x, P2.x, TAx ComparatorA see NoteVRefVT vs Temperature, VCC = 3 V, C1121 VRefVT vs Temperature, VCC = 2.2 V, C1121PUC/POR CAF CaonRAM Parameter MIN NOM MAX UnitDcoclk DCOVariance Max DCO StepsWake-up from lower power modes LPMx Principle characteristics of the DCOJTAG/programming Port P1, P1.0 to P1.3, input/output with Schmitt-trigger Input/output schematicGND P1DIR.5 P1OUT.5 P1DIR.4 P1OUT.4 SmclkP1IFG.4 P1IES.4 P1IFG.5 P1IES.5Port P2, P2.0 to P2.2, input/output with Schmitt-trigger CAPD.XP2IFG.3 P1IES.3 Port P2, P2.3 to P2.4, input/output with Schmitt-triggerP2DIR.3 P2OUT.3 P2DIR.4 P2OUT.4P2OUT.5 P2SEL.5 VCCP2DIR.5 P2IRQ.5Port P2, unbonded bits P2.6 and P2.7 Plastic SMALL-OUTLINE Package Pins DIM MAXDW R-PDSO-G PIN ShownPW R-PDSO-G Plastic SMALL-OUTLINE Package Pins ShownPins DIM MAX MIN 15 NOM Gage Plane Seating Plane 20 MAXImportant Notice