Texas Instruments MSP430x11x1 warranty Memory organization, Boot ROM containing bootstrap loader

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MSP430x11x1

MIXED SIGNAL MICROCONTROLLER

SLAS241C ± SEPTEMBER 1999 ± REVISED JUNE 2000

memory organization

 

MSP430C1111

 

FFFFh

 

 

FFFFh

Int. Vector

FFE0h

FFE0h

 

 

FFDFh

2 KB ROM

FFDFh

 

 

F800h

 

 

F000h

 

 

 

 

 

 

 

02FFh

027Fh

 

 

128B RAM

0200h

0200h

 

01FFh

16b Per.

01FFh

0100h

0100h

 

00FFh

8b Per.

00FFh

0010h

0010h

 

000Fh

SFR

000Fh

0000h

 

0000h

 

MSP430C1121

 

MSP430F1101

 

 

 

FFFFh

 

 

FFFFh

Int. Vector

 

Int. Vector

 

 

FFE0h

 

FFE0h

 

 

 

 

 

 

FFDFh

1 KB Flash

 

FFDFh

 

 

 

 

4 KB

 

FC00h

Segment0,1

 

 

 

 

 

 

 

ROM

 

10FFh

 

 

F000h

 

 

128B Flash

 

10FFh

 

 

 

 

 

 

 

 

 

1080h

SegmentA

 

 

 

0FFFh

 

 

1000h

 

 

1 KB

 

 

 

 

 

 

 

 

 

0C00h

Boot ROM

 

0FFFh

 

 

 

 

 

 

 

 

 

0C00h

 

 

 

 

 

02FFh

256B RAM

 

027Fh

 

 

 

 

 

 

 

128B RAM

 

 

 

 

 

 

 

 

0200h

 

0200h

 

 

 

 

16b Per.

 

01FFh

16b Per.

 

01FFh

 

0100h

 

0100h

 

 

 

 

8b Per.

 

00FFh

8b Per.

 

00FFh

 

0010h

 

0010h

 

 

 

 

SFR

 

000Fh

SFR

 

000Fh

 

 

0000h

 

 

0000h

 

 

 

 

MSP430F1121

 

 

 

 

 

Int. Vector

 

 

 

 

 

 

4 KB

 

Main

Flash

 

Segment0±7

 

Memory

 

 

 

 

 

 

 

2 128B

 

 

Information

Flash

 

 

Memory

SegmentA,B

 

 

 

 

 

 

1 KB

 

 

Boot ROM

 

 

 

 

 

 

 

 

 

 

256B RAM

 

 

 

 

 

 

16b Per.

 

 

 

 

 

 

8b Per.

 

 

 

 

 

 

SFR

 

 

 

 

 

 

boot ROM containing bootstrap loader

The intention of the bootstrap loader is to download data into the flash memory module. Various write, read, and erase operations are needed for a proper download environment. The bootstrap loader is only available on F devices.

functions of the bootstrap loader:

Definition of read:

apply and transmit data of peripheral registers or memory to pin P1.1 (BSLTX)

write:

read data from pin P2.2 (BSLRX) and write them into flash memory

unprotected functions

Mass erase, erase of the main memory (Segment0 to Segment7)

Access to the MSP430 via the bootstrap loader is protected. It must be enabled before any protected function can be performed. The 256 bits in 0FFE0h to 0FFFFh provide the access key.

protected functions

All protected functions can be executed only if the access is enabled.

DWrite/program byte into flash memory; Parameters passed are start address and number of bytes (the segment-write feature of the flash memory is not supported and not useful with the UART protocol).

DSegment erase of Segment0 to Segment7 in the main memory and segment erase of SegmentA and SegmentB in the information memory.

DRead all data in main memory and information memory.

DRead and write to all byte peripheral modules and RAM.

DModify PC and start program execution immediately.

NOTE:

Unauthorized readout of code and data is prevented by the user's definition of the data in the interrupt memory locations.

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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Contents MSP430x11x1 DescriptionTssop Available Options Packaged Devices Functional block diagramPIN Sowb PIN Tssop Pulldown resistor of 30 k Ω is needed on F11x1Short-form description Terminal FunctionsProcessing unit Terminal Description NameCPU Address Mode DescriptionsInstruction set Instruction Word FormatsOperation modes and interrupts Low-power consumption capabilitiesSCG1 Status register R2SCG0 SCG1 SCG0Caifg Interrupt vector addressesWdtifg CCIFG1, CCIFG2, TaifgWdtifg Special function registersOfifg NmiifgBoot ROM containing bootstrap loader Functions of the bootstrap loaderMemory organization Hardware resources used for serial input/output Features of the bootstrap loader areWDT VCC RST/NMI PIN Test PINVCC Bootstrap loader StartsTest InternalFlash memory control register FCTL1 Flash memoryFlash memory, timing generator, control register FCTL2 Erase 0128h, bit1, Erase a segmentWRT FN0±FN5 Flash memory control register FCTL3SSEL0, SSEL1 AclkKeyv BusyAccvifg WaitFlash memory, interrupt and security key violation LockEmex PUC AccvPOR NmirsOscillator and system clock PeripheralsDigital I/O Clock SignalsTimerA Three capture/compare registers Watchdog timerTimerA, MSP430x11x1 Configuration TimerA 3 capture/compare registersComparatorA CAF CaoutCACTL2.4 CATCTL2.7CACTL1 Slope a/d conversionCaex Caon Caies Caifg Rsel REF1 REF0 CACTL2Peripherals with Word Access Peripherals with Byte AccessPeripheral file map Absolute maximum ratings² Recommended operating conditionsMIN NOM MAX Units Frequency vs Supply Voltage MSP430x11x1 DevicesIAM Parameter Test Conditions MIN TYP MAX UnitILPM2 ILPM3Leakage current Outputs Port 1 to P2 P1.0 to P1.7, P2.0 to P2.5Inputs Px.x, TAx Internal signals TAx, Smclk at TimerAParameter Test Conditions VCC MIN TYP MAX Unit Port P1, P2 P1.x to P2.xComparatorA see Note Outputs P1.x, P2.x, TAxVRefVT vs Temperature, VCC = 2.2 V, C1121 VRefVT vs Temperature, VCC = 3 V, C1121CAF Caon PUC/PORParameter MIN NOM MAX Unit RAMVariance Max DCODcoclk DCO StepsPrinciple characteristics of the DCO Wake-up from lower power modes LPMxJTAG/programming Input/output schematic Port P1, P1.0 to P1.3, input/output with Schmitt-triggerGND P1IFG.4 P1IES.4 P1DIR.4 P1OUT.4 SmclkP1DIR.5 P1OUT.5 P1IFG.5 P1IES.5CAPD.X Port P2, P2.0 to P2.2, input/output with Schmitt-triggerP2DIR.3 P2OUT.3 Port P2, P2.3 to P2.4, input/output with Schmitt-triggerP2IFG.3 P1IES.3 P2DIR.4 P2OUT.4P2DIR.5 P2SEL.5 VCCP2OUT.5 P2IRQ.5Port P2, unbonded bits P2.6 and P2.7 DW R-PDSO-G Pins DIM MAXPlastic SMALL-OUTLINE Package PIN ShownPins DIM MAX MIN Pins ShownPW R-PDSO-G Plastic SMALL-OUTLINE Package 15 NOM Gage Plane Seating Plane 20 MAXImportant Notice