Texas Instruments MSP430x11x1 warranty Port P2, P2.3 to P2.4, input/output with Schmitt-trigger

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MSP430x11x1

MIXED SIGNAL MICROCONTROLLER

SLAS241C ± SEPTEMBER 1999 ± REVISED JUNE 2000

APPLICATION INFORMATION

Port P2, P2.3 to P2.4, input/output with Schmitt-trigger

P2SEL.3	0		VCC
P2DIR.3	0	0: Input
P2DIR.3		0: Input
Direction Control	1	1: Output	See Note 27
From Module		1: Output
From Module		Pad Logic
P2OUT.3	0	Pad Logic	See Note 28	P2.3
P2OUT.3				P2.3
Module X	1
Module X
OUT			See Note 28

						See Note 27
P2IN.3					Bus Keeper	GND
	EN				Bus Keeper
	EN
Module X IN	D
P2IRQ.3	P2IE.3	EN	Interrupt
			Interrupt
	Q		Edge
	Q		Edge			CAPD.3
	P2IFG.3	Set	Select			CAPD.3
	P2IFG.3	Set
					Comparator_A
	Interrupt				Comparator_A	CAREF	P2CA CAEX
						CAREF	P2CA CAEX

	Flag		P2IES.3	P2SEL.3
					CAF
	CCI1B					+
						_
					0 V

Interrupt	P2IES.4			P2SEL.4
Flag						CAREF		Reference Block
Flag						CAREF		Reference Block

	P2IFG.4	Set	Interrupt	CAPD.4
	Q		Edge	CAPD.4
	Q	EN	Edge
P2IRQ.4	P2IE.4	EN	Select
			Select

Module X IN	D
	EN			Bus Keeper
P2IN.4				Bus Keeper
P2IN.4				VCC
				See Note 27
				See Note 28

Module X OUT	1

P2OUT.4	0	Pad Logic	See Note 28	P2.4


Direction Control		1: Output
From Module	1		See Note 27

P2DIR.4	0	0: Input

P2SEL.4			GND

APPLICATION INFORMATION

PnSel.x	PnDIR.x	Direction	PnOUT.x	Module X OUT	PnIN.x	Module X IN	PnIE.x	PnIFG.x	PnIES.x
		control from module

P2Sel.3	P2DIR.3	P2DIR.3	P2OUT.3	Out1 signal²	P2IN.3	unused	P2IE.3	P2IFG.3	P1IES.3
P2Sel.4	P2DIR.4	P2DIR.4	P2OUT.4	Out2 signal²	P2IN.4	unused	P2IE.4	P2IFG.4	P1IES.4

²Signal from Timer_A

NOTES: 27. Optional selection of pullup or pulldown resistors with ROM (masked) versions.

28. Fuses for optional pullup and pulldown resistors can only be programmed at the factory (ROM versions only).

40	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

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Contents Description MSP430x11x1Tssop Functional block diagram Available Options Packaged DevicesPIN Sowb PIN Tssop Pulldown resistor of 30 k Ω is needed on F11x1Terminal Functions Short-form descriptionProcessing unit Terminal Description NameAddress Mode Descriptions CPUInstruction set Instruction Word FormatsLow-power consumption capabilities Operation modes and interruptsStatus register R2 SCG1SCG0 SCG1 SCG0Interrupt vector addresses CaifgWdtifg CCIFG1, CCIFG2, TaifgSpecial function registers WdtifgOfifg NmiifgFunctions of the bootstrap loader Boot ROM containing bootstrap loaderMemory organization Features of the bootstrap loader are Hardware resources used for serial input/outputWDT VCC RST/NMI PIN Test PINBootstrap loader Starts VCCTest InternalFlash memory Flash memory control register FCTL1Erase 0128h, bit1, Erase a segment Flash memory, timing generator, control register FCTL2WRT Flash memory control register FCTL3 FN0±FN5SSEL0, SSEL1 AclkBusy KeyvAccvifg WaitLock Flash memory, interrupt and security key violationEmex Accv PUCPOR NmirsPeripherals Oscillator and system clockClock Signals Digital I/OWatchdog timer TimerA Three capture/compare registersTimerA 3 capture/compare registers TimerA, MSP430x11x1 ConfigurationComparatorA Caout CAFCACTL2.4 CATCTL2.7Slope a/d conversion CACTL1Caex Caon Caies Caifg Rsel REF1 REF0 CACTL2Peripherals with Byte Access Peripherals with Word AccessPeripheral file map Recommended operating conditions Absolute maximum ratings²MIN NOM MAX Units MSP430x11x1 Devices Frequency vs Supply VoltageParameter Test Conditions MIN TYP MAX Unit IAMILPM2 ILPM3Outputs Port 1 to P2 P1.0 to P1.7, P2.0 to P2.5 Leakage currentInternal signals TAx, Smclk at TimerA Inputs Px.x, TAxParameter Test Conditions VCC MIN TYP MAX Unit Port P1, P2 P1.x to P2.xOutputs P1.x, P2.x, TAx ComparatorA see NoteVRefVT vs Temperature, VCC = 3 V, C1121 VRefVT vs Temperature, VCC = 2.2 V, C1121PUC/POR CAF CaonRAM Parameter MIN NOM MAX UnitDCO Variance MaxDcoclk DCO StepsWake-up from lower power modes LPMx Principle characteristics of the DCOJTAG/programming Port P1, P1.0 to P1.3, input/output with Schmitt-trigger Input/output schematicGND P1DIR.4 P1OUT.4 Smclk P1IFG.4 P1IES.4P1DIR.5 P1OUT.5 P1IFG.5 P1IES.5Port P2, P2.0 to P2.2, input/output with Schmitt-trigger CAPD.XPort P2, P2.3 to P2.4, input/output with Schmitt-trigger P2DIR.3 P2OUT.3P2IFG.3 P1IES.3 P2DIR.4 P2OUT.4P2SEL.5 VCC P2DIR.5P2OUT.5 P2IRQ.5Port P2, unbonded bits P2.6 and P2.7 Pins DIM MAX DW R-PDSO-GPlastic SMALL-OUTLINE Package PIN ShownPins Shown Pins DIM MAX MINPW R-PDSO-G Plastic SMALL-OUTLINE Package 15 NOM Gage Plane Seating Plane 20 MAXImportant Notice