Texas Instruments MSP430x11x1 warranty Inputs Px.x, TAx, Internal signals TAx, Smclk at TimerA

Page 30

MSP430x11x1

MIXED SIGNAL MICROCONTROLLER

SLAS241C ± SEPTEMBER 1999 ± REVISED JUNE 2000

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued)

optional resistors, individually programmable with ROM code (see Note 13)

 

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

 

 

 

 

 

 

 

R(opt1)

 

 

2.5

5

10

kΩ

R(opt2)

 

 

3.8

7.7

15

kΩ

R(opt3)

 

 

7.6

15

31

kΩ

R(opt4)

 

 

11.5

23

46

kΩ

R(opt5)

Resistors, individually programmable with ROM code, all port pins,

VCC = 2.2 V/3 V

23

45

90

kΩ

R(opt6)

values applicable for pulldown and pullup

46

90

180

kΩ

 

 

 

R(opt7)

 

 

70

140

280

kΩ

R(opt8)

 

 

115

230

460

kΩ

R(opt9)

 

 

160

320

640

kΩ

R(opt10)

 

 

205

420

830

kΩ

NOTE 13: Optional resistors Roptx for pulldown or pullup are not available in standard flash memory device MSP430F11x1.

inputs Px.x, TAx

 

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP MAX

UNIT

 

 

 

 

 

 

 

 

 

Port P1, P2: P1.x to P2.x,

2.2 V/3 V

1.5

 

cycle

t(int)

External interrupt timing

 

 

 

 

External trigger signal for the interrupt flag,

2.2 V

62

 

ns

 

 

(see Note 14)

3 V

50

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2.2 V/3 V

1.5

 

cycle

t(cap)

Timer_A, capture timing

TA0, TA1, TA2. (see Note 15)

 

 

 

 

2.2 V

62

 

ns

 

 

 

3 V

50

 

 

 

 

 

 

NOTES: 14. The external signal sets the interrupt flag every time the minimum tint cycle and time parameters are met. It may be set even with trigger signals shorter than tint. Both the cycle and timing specifications must be met to ensure the flag is set. tint is measured in MCLK cycles.

15.The external capture signal triggers the capture event every time when the minimum tcap cycles and time parameters are met. A capture may be triggered with capture signals even shorter than tcap. Both the cycle and timing specifications must be met to ensure a correct capture of the 16-bit timer value and to ensure the flag is set.

internal signals TAx, SMCLK at Timer_A

 

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX

UNIT

 

 

 

 

 

 

 

 

f(IN)

Input frequency

Internal TA0, TA1, TA2, tH = tL

2.2 V

 

 

8

MHz

 

 

 

 

3 V

 

 

10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

f(TAint)

Timer_A clock frequency

Internally, SMCLK signal applied

2.2 V/3 V

dc

 

fSystem

 

30

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Image 30
Contents MSP430x11x1 DescriptionTssop PIN Sowb PIN Tssop Functional block diagramAvailable Options Packaged Devices Pulldown resistor of 30 k Ω is needed on F11x1Processing unit Terminal FunctionsShort-form description Terminal Description NameInstruction set Address Mode DescriptionsCPU Instruction Word FormatsLow-power consumption capabilities Operation modes and interruptsSCG0 Status register R2SCG1 SCG1 SCG0Wdtifg Interrupt vector addressesCaifg CCIFG1, CCIFG2, TaifgOfifg Special function registersWdtifg NmiifgBoot ROM containing bootstrap loader Functions of the bootstrap loaderMemory organization WDT Features of the bootstrap loader areHardware resources used for serial input/output VCC RST/NMI PIN Test PINTest Bootstrap loader StartsVCC InternalFlash memory Flash memory control register FCTL1Flash memory, timing generator, control register FCTL2 Erase 0128h, bit1, Erase a segmentWRT SSEL0, SSEL1 Flash memory control register FCTL3FN0±FN5 AclkAccvifg BusyKeyv WaitFlash memory, interrupt and security key violation LockEmex POR AccvPUC NmirsPeripherals Oscillator and system clockClock Signals Digital I/OWatchdog timer TimerA Three capture/compare registersTimerA 3 capture/compare registers TimerA, MSP430x11x1 ConfigurationComparatorA CACTL2.4 CaoutCAF CATCTL2.7Caex Caon Caies Caifg Rsel REF1 REF0 Slope a/d conversionCACTL1 CACTL2Peripherals with Word Access Peripherals with Byte AccessPeripheral file map Absolute maximum ratings² Recommended operating conditionsMIN NOM MAX Units MSP430x11x1 Devices Frequency vs Supply VoltageILPM2 Parameter Test Conditions MIN TYP MAX UnitIAM ILPM3Outputs Port 1 to P2 P1.0 to P1.7, P2.0 to P2.5 Leakage currentParameter Test Conditions VCC MIN TYP MAX Unit Internal signals TAx, Smclk at TimerAInputs Px.x, TAx Port P1, P2 P1.x to P2.xOutputs P1.x, P2.x, TAx ComparatorA see NoteVRefVT vs Temperature, VCC = 3 V, C1121 VRefVT vs Temperature, VCC = 2.2 V, C1121PUC/POR CAF CaonRAM Parameter MIN NOM MAX UnitDcoclk DCOVariance Max DCO StepsPrinciple characteristics of the DCO Wake-up from lower power modes LPMxJTAG/programming Input/output schematic Port P1, P1.0 to P1.3, input/output with Schmitt-triggerGND P1DIR.5 P1OUT.5 P1DIR.4 P1OUT.4 SmclkP1IFG.4 P1IES.4 P1IFG.5 P1IES.5Port P2, P2.0 to P2.2, input/output with Schmitt-trigger CAPD.XP2IFG.3 P1IES.3 Port P2, P2.3 to P2.4, input/output with Schmitt-triggerP2DIR.3 P2OUT.3 P2DIR.4 P2OUT.4P2OUT.5 P2SEL.5 VCCP2DIR.5 P2IRQ.5Port P2, unbonded bits P2.6 and P2.7 Plastic SMALL-OUTLINE Package Pins DIM MAXDW R-PDSO-G PIN ShownPW R-PDSO-G Plastic SMALL-OUTLINE Package Pins ShownPins DIM MAX MIN 15 NOM Gage Plane Seating Plane 20 MAXImportant Notice