Texas Instruments MSP430x11x1 warranty Port P2, unbonded bits P2.6 and P2.7

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MSP430x11x1

MIXED SIGNAL MICROCONTROLLER

SLAS241C ± SEPTEMBER 1999 ± REVISED JUNE 2000

APPLICATION INFORMATION

Port P2, unbonded bits P2.6 and P2.7

P2SEL.x

P2DIR.x

Direction Control From Module

P2OUT.x

Module X OUT

P2IN.x

Module X IN

P2IRQ.x

0

0:

Input

 

1:

Output

1

0

1

Node Is Reset With PUC

EN

Bus Keeper

D

P2IE.x

EN

Interrupt

PUC

 

 

 

Edge

 

P2IFG.x

Q

 

Set

Select

 

 

 

 

 

Interrupt

P2IES.x

 

 

Flag

 

 

 

 

 

 

P2SEL.x

 

NOTE: x = Bit/identifier, 6 to 7 for port P2 without external pins

 

 

Direction

 

 

 

 

 

 

 

P2Sel.x

P2DIR.x

control from

P2OUT.x

Module X OUT

P2IN.x

Module X IN

P2IE.x

P2IFG.x

P2IES.x

 

 

module

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P2Sel.6

P2DIR.6

P2DIR.6

P2OUT.6

VSS

P2IN.6

unused

P2IE.6

P2IFG.6

P2IES.6

 

 

 

 

 

 

 

 

 

 

P2Sel.7

P2DIR.7

P2DIR.7

P2OUT.7

VSS

P2IN.7

unused

P2IE.7

P2IFG.7

P2IES.7

NOTE: A good use of the unbonded bits 6 and 7 of port P2 is to use the interrupt flags. The interrupt flags can not be influenced from any signal other than from software. They work then as a soft interrupt.

JTAG fuse check mode

MSP430 devices that have the fuse on the TEST terminal have a fuse check mode that tests the continuity of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check current can flow from the TEST pin to ground if the fuse is not burned. Care must be taken to avoid accidentally activating the fuse check mode and increasing overall system power consumption.

When the TEST pin is taken back low after a test or programming session, the fuse check mode and sense currents are terminated.

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Contents MSP430x11x1 DescriptionTssop PIN Sowb PIN Tssop Functional block diagramAvailable Options Packaged Devices Pulldown resistor of 30 k Ω is needed on F11x1Processing unit Terminal FunctionsShort-form description Terminal Description NameInstruction set Address Mode DescriptionsCPU Instruction Word FormatsLow-power consumption capabilities Operation modes and interruptsSCG0 Status register R2SCG1 SCG1 SCG0Wdtifg Interrupt vector addressesCaifg CCIFG1, CCIFG2, TaifgOfifg Special function registersWdtifg NmiifgBoot ROM containing bootstrap loader Functions of the bootstrap loaderMemory organization WDT Features of the bootstrap loader areHardware resources used for serial input/output VCC RST/NMI PIN Test PINTest Bootstrap loader StartsVCC InternalFlash memory Flash memory control register FCTL1Flash memory, timing generator, control register FCTL2 Erase 0128h, bit1, Erase a segmentWRT SSEL0, SSEL1 Flash memory control register FCTL3FN0±FN5 AclkAccvifg BusyKeyv WaitFlash memory, interrupt and security key violation LockEmex POR AccvPUC NmirsPeripherals Oscillator and system clockClock Signals Digital I/OWatchdog timer TimerA Three capture/compare registersTimerA 3 capture/compare registers TimerA, MSP430x11x1 ConfigurationComparatorA CACTL2.4 CaoutCAF CATCTL2.7Caex Caon Caies Caifg Rsel REF1 REF0 Slope a/d conversionCACTL1 CACTL2Peripherals with Word Access Peripherals with Byte AccessPeripheral file map Absolute maximum ratings² Recommended operating conditionsMIN NOM MAX Units MSP430x11x1 Devices Frequency vs Supply VoltageILPM2 Parameter Test Conditions MIN TYP MAX UnitIAM ILPM3Outputs Port 1 to P2 P1.0 to P1.7, P2.0 to P2.5 Leakage currentParameter Test Conditions VCC MIN TYP MAX Unit Internal signals TAx, Smclk at TimerAInputs Px.x, TAx Port P1, P2 P1.x to P2.xOutputs P1.x, P2.x, TAx ComparatorA see NoteVRefVT vs Temperature, VCC = 3 V, C1121 VRefVT vs Temperature, VCC = 2.2 V, C1121PUC/POR CAF CaonRAM Parameter MIN NOM MAX UnitDcoclk DCOVariance Max DCO StepsPrinciple characteristics of the DCO Wake-up from lower power modes LPMxJTAG/programming Input/output schematic Port P1, P1.0 to P1.3, input/output with Schmitt-triggerGND P1DIR.5 P1OUT.5 P1DIR.4 P1OUT.4 SmclkP1IFG.4 P1IES.4 P1IFG.5 P1IES.5Port P2, P2.0 to P2.2, input/output with Schmitt-trigger CAPD.XP2IFG.3 P1IES.3 Port P2, P2.3 to P2.4, input/output with Schmitt-triggerP2DIR.3 P2OUT.3 P2DIR.4 P2OUT.4P2OUT.5 P2SEL.5 VCCP2DIR.5 P2IRQ.5Port P2, unbonded bits P2.6 and P2.7 Plastic SMALL-OUTLINE Package Pins DIM MAXDW R-PDSO-G PIN ShownPW R-PDSO-G Plastic SMALL-OUTLINE Package Pins ShownPins DIM MAX MIN 15 NOM Gage Plane Seating Plane 20 MAXImportant Notice