Texas Instruments MSP430x11x1 warranty PW R-PDSO-G Plastic SMALL-OUTLINE Package, Pins Shown

Page 44

MSP430x11x1

MIXED SIGNAL MICROCONTROLLER

SLAS241C ± SEPTEMBER 1999 ± REVISED JUNE 2000

MECHANICAL DATA

PW (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,65

0,30

0,10

M

 

 

 

0,19

 

 

 

 

 

 

 

 

 

14

8

 

 

 

 

 

 

 

 

 

 

0,15 NOM

 

 

4,50

6,60

 

 

 

 

 

4,30

6,20

 

 

 

 

 

 

 

 

 

Gage Plane

 

 

 

 

 

 

0,25

1

7

 

 

 

0°± 8°

 

A

 

 

 

 

 

 

 

 

 

 

0,75

 

 

 

 

 

 

0,50

 

 

Seating Plane

 

 

 

1,20 MAX

0,15

0,10

 

 

 

0,05

 

 

 

 

 

 

 

 

 

PINS **

14

16

20

24

28

DIM

8

 

 

 

 

 

 

A MAX

3,10

5,10

5,10

6,60

7,90

9,80

A MIN

2,90

4,90

4,90

6,40

7,70

9,60

 

 

 

 

 

 

4040064/F 01/97

NOTES: A. All linear dimensions are in millimeters.

B.This drawing is subject to change without notice.

C.Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D.Falls within JEDEC MO-153

44

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

Image 44
Contents Tssop MSP430x11x1Description Functional block diagram Available Options Packaged DevicesPIN Sowb PIN Tssop Pulldown resistor of 30 k Ω is needed on F11x1Terminal Functions Short-form descriptionProcessing unit Terminal Description NameAddress Mode Descriptions CPUInstruction set Instruction Word FormatsLow-power consumption capabilities Operation modes and interruptsStatus register R2 SCG1SCG0 SCG1 SCG0Interrupt vector addresses CaifgWdtifg CCIFG1, CCIFG2, TaifgSpecial function registers WdtifgOfifg NmiifgMemory organization Boot ROM containing bootstrap loaderFunctions of the bootstrap loader Features of the bootstrap loader are Hardware resources used for serial input/outputWDT VCC RST/NMI PIN Test PINBootstrap loader Starts VCCTest InternalFlash memory Flash memory control register FCTL1WRT Flash memory, timing generator, control register FCTL2Erase 0128h, bit1, Erase a segment Flash memory control register FCTL3 FN0±FN5SSEL0, SSEL1 AclkBusy KeyvAccvifg WaitEmex Flash memory, interrupt and security key violationLock Accv PUCPOR NmirsPeripherals Oscillator and system clockClock Signals Digital I/OWatchdog timer TimerA Three capture/compare registersTimerA 3 capture/compare registers TimerA, MSP430x11x1 ConfigurationComparatorA Caout CAFCACTL2.4 CATCTL2.7Slope a/d conversion CACTL1Caex Caon Caies Caifg Rsel REF1 REF0 CACTL2Peripheral file map Peripherals with Word AccessPeripherals with Byte Access MIN NOM MAX Units Absolute maximum ratings²Recommended operating conditions MSP430x11x1 Devices Frequency vs Supply VoltageParameter Test Conditions MIN TYP MAX Unit IAMILPM2 ILPM3Outputs Port 1 to P2 P1.0 to P1.7, P2.0 to P2.5 Leakage currentInternal signals TAx, Smclk at TimerA Inputs Px.x, TAxParameter Test Conditions VCC MIN TYP MAX Unit Port P1, P2 P1.x to P2.xOutputs P1.x, P2.x, TAx ComparatorA see NoteVRefVT vs Temperature, VCC = 3 V, C1121 VRefVT vs Temperature, VCC = 2.2 V, C1121PUC/POR CAF CaonRAM Parameter MIN NOM MAX UnitDCO Variance MaxDcoclk DCO StepsJTAG/programming Principle characteristics of the DCOWake-up from lower power modes LPMx GND Input/output schematicPort P1, P1.0 to P1.3, input/output with Schmitt-trigger P1DIR.4 P1OUT.4 Smclk P1IFG.4 P1IES.4P1DIR.5 P1OUT.5 P1IFG.5 P1IES.5Port P2, P2.0 to P2.2, input/output with Schmitt-trigger CAPD.XPort P2, P2.3 to P2.4, input/output with Schmitt-trigger P2DIR.3 P2OUT.3P2IFG.3 P1IES.3 P2DIR.4 P2OUT.4P2SEL.5 VCC P2DIR.5P2OUT.5 P2IRQ.5Port P2, unbonded bits P2.6 and P2.7 Pins DIM MAX DW R-PDSO-GPlastic SMALL-OUTLINE Package PIN ShownPins Shown Pins DIM MAX MINPW R-PDSO-G Plastic SMALL-OUTLINE Package 15 NOM Gage Plane Seating Plane 20 MAXImportant Notice