Texas Instruments MSP430x11x1 warranty Accv, Puc, Por, Nmirs, Irqa, Timsel

Page 17

MSP430x11x1

MIXED SIGNAL MICROCONTROLLER

SLAS241C ± SEPTEMBER 1999 ± REVISED JUNE 2000

ACCV

ACCVIFG
S
FCTL1.1
ACCVIE				Flash Module
				Flash Module
IE1.5				Flash Module
Clear				Flash Module
				Flash Module
PUC
RST/NMI
				POR	PUC
			KEYV		VCC
						PUC
				System Reset
				Generator
						POR
NMIFG
S						NMIRS
IFG1.4						NMIRS
IFG1.4
Clear	TMSEL	NMI	WDTQn	EQU	PUC	POR
NMIES	TMSEL	NMI	WDTQn	EQU	PUC	POR
PUC
NMIIE
			S	WDTIFG
IE1.4			S			IRQ
IE1.4
Clear		IFG1.0
Clear		IFG1.0
			Clear
PUC		WDT
Counter
OSCFault		POR
		POR
OFIFG
S
IFG1.1
		IRQA
OFIF		TIMSEL
OFIF
				WDTIE
IE1.1
Clear		IE1.0
		IE1.0	Clear
NMI_IRQA			Clear
PUC
Watchdog Timer Module			PUC
Watchdog Timer Module

IRQA: Interrupt Request Accepted

Figure 2. Block Diagram of NMI Interrupt Sources

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Image 17

Contents Tssop MSP430x11x1Description Available Options Packaged Devices Functional block diagramPIN Sowb PIN Tssop Pulldown resistor of 30 k Ω is needed on F11x1Short-form description Terminal FunctionsProcessing unit Terminal Description NameCPU Address Mode DescriptionsInstruction set Instruction Word FormatsOperation modes and interrupts Low-power consumption capabilitiesSCG1 Status register R2SCG0 SCG1 SCG0Caifg Interrupt vector addressesWdtifg CCIFG1, CCIFG2, TaifgWdtifg Special function registersOfifg NmiifgMemory organization Boot ROM containing bootstrap loaderFunctions of the bootstrap loader Hardware resources used for serial input/output Features of the bootstrap loader areWDT VCC RST/NMI PIN Test PINVCC Bootstrap loader StartsTest InternalFlash memory control register FCTL1 Flash memoryWRT Flash memory, timing generator, control register FCTL2Erase 0128h, bit1, Erase a segment FN0±FN5 Flash memory control register FCTL3SSEL0, SSEL1 AclkKeyv BusyAccvifg WaitEmex Flash memory, interrupt and security key violationLock PUC AccvPOR NmirsOscillator and system clock PeripheralsDigital I/O Clock SignalsTimerA Three capture/compare registers Watchdog timerTimerA, MSP430x11x1 Configuration TimerA 3 capture/compare registersComparatorA CAF CaoutCACTL2.4 CATCTL2.7CACTL1 Slope a/d conversionCaex Caon Caies Caifg Rsel REF1 REF0 CACTL2Peripheral file map Peripherals with Word AccessPeripherals with Byte Access MIN NOM MAX Units Absolute maximum ratings²Recommended operating conditions Frequency vs Supply Voltage MSP430x11x1 DevicesIAM Parameter Test Conditions MIN TYP MAX UnitILPM2 ILPM3Leakage current Outputs Port 1 to P2 P1.0 to P1.7, P2.0 to P2.5Inputs Px.x, TAx Internal signals TAx, Smclk at TimerAParameter Test Conditions VCC MIN TYP MAX Unit Port P1, P2 P1.x to P2.xComparatorA see Note Outputs P1.x, P2.x, TAxVRefVT vs Temperature, VCC = 2.2 V, C1121 VRefVT vs Temperature, VCC = 3 V, C1121CAF Caon PUC/PORParameter MIN NOM MAX Unit RAMVariance Max DCODcoclk DCO StepsJTAG/programming Principle characteristics of the DCOWake-up from lower power modes LPMx GND Input/output schematicPort P1, P1.0 to P1.3, input/output with Schmitt-trigger P1IFG.4 P1IES.4 P1DIR.4 P1OUT.4 SmclkP1DIR.5 P1OUT.5 P1IFG.5 P1IES.5CAPD.X Port P2, P2.0 to P2.2, input/output with Schmitt-triggerP2DIR.3 P2OUT.3 Port P2, P2.3 to P2.4, input/output with Schmitt-triggerP2IFG.3 P1IES.3 P2DIR.4 P2OUT.4P2DIR.5 P2SEL.5 VCCP2OUT.5 P2IRQ.5Port P2, unbonded bits P2.6 and P2.7 DW R-PDSO-G Pins DIM MAXPlastic SMALL-OUTLINE Package PIN ShownPins DIM MAX MIN Pins ShownPW R-PDSO-G Plastic SMALL-OUTLINE Package 15 NOM Gage Plane Seating Plane 20 MAXImportant Notice

MIXED SIGNAL MICROCONTROLLER

ACCV

PUC

POR

NMIRS

IRQ

IRQA

TIMSEL

Figure 2. Block Diagram of NMI Interrupt Sources