Texas Instruments MSP430x11x1 Caout, Caf, CACTL2.4, CATCTL2.7, Caifg, Caies, Caon, Caref

Page 23

		MSP430x11x1
		MIXED SIGNAL MICROCONTROLLER
		SLAS241C ± SEPTEMBER 1999 ± REVISED JUNE 2000

Comparator_A (continued)
The control bits are:
CAOUT,	05Ah, bit0,	Comparator output
CAF,	05Ah, bit1,	The comparator output is transparent or fed through a small filter
CA0,	05Ah, bit2,	0: Pin P2.3/CA0/TA1 is not connected to Comparator_A.
		1: Pin P2.3/CA0/TA1 is connected to Comparator_A.
CA1,	05Ah, bit3,	0: Pin P2.4/CA1/TA2 is not connected to Comparator_A.
		1: Pin P2.4/CA1/TA2 is connected to Comparator_A.
CACTL2.4	05Ah, bit4,	Bits are implemented but do not control any hardware in this device.
to
CATCTL2.7	05Ah, bit7,
CAIFG,	059h, bit0,	Comparator_A interrupt flag
CAIE,	059h, bit1,	Comparator_A interrupt enable
CAIES,	059h, bit2,	Comparator_A interrupt edge select bit
		0: The rising edge sets the Comparator_A interrupt flag CAIFG
		1: The falling edge set the Comparator_A interrupt flag CAIFG
CAON,	059h, bit3,	The comparator is switched on.
CAREF,	059h, bit4,5,	Comparator_A reference
		0: Internal reference is switched off, an external reference can be applied.
		1: 0.25 ⋅ VCC reference selected.
		2: 0.50 ⋅ VCC reference selected.
		3: A diode reference selected.
CARSEL,	059h, bit6,	An internal reference VCAREF, selected by CAREF bits, can be applied to
		signal path CA0 or CA1. The signal VCAREF is only driven by a voltage
		source if the value of CAREF control bits is 1, 2, or 3.
CAEX,	059h, bit7,	The comparator inputs are exchanged, used to measure and compensate
		the offset of the comparator.

Eight additional bits are implemented into the Comparator_A module and enable the SW to switch off the input buffer of port P2. A CMOS input buffer would dissipate supply current when the input is not near VSS or VCC. Comparator_A port disable control bits CAPD0 to CAPD7 are initially reset, and the port input buffer is active. The port input buffer is disabled if the appropriate control bit is set.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

23

Image 23

Contents Tssop MSP430x11x1Description Pulldown resistor of 30 k Ω is needed on F11x1 Functional block diagramAvailable Options Packaged Devices PIN Sowb PIN TssopTerminal Description Name Terminal FunctionsShort-form description Processing unitInstruction Word Formats Address Mode DescriptionsCPU Instruction setOperation modes and interrupts Low-power consumption capabilitiesSCG1 SCG0 Status register R2SCG1 SCG0CCIFG1, CCIFG2, Taifg Interrupt vector addressesCaifg WdtifgNmiifg Special function registersWdtifg OfifgMemory organization Boot ROM containing bootstrap loaderFunctions of the bootstrap loader VCC RST/NMI PIN Test PIN Features of the bootstrap loader areHardware resources used for serial input/output WDTInternal Bootstrap loader StartsVCC TestFlash memory control register FCTL1 Flash memoryWRT Flash memory, timing generator, control register FCTL2Erase 0128h, bit1, Erase a segment Aclk Flash memory control register FCTL3FN0±FN5 SSEL0, SSEL1Wait BusyKeyv AccvifgEmex Flash memory, interrupt and security key violationLock Nmirs AccvPUC POROscillator and system clock PeripheralsDigital I/O Clock SignalsTimerA Three capture/compare registers Watchdog timerTimerA, MSP430x11x1 Configuration TimerA 3 capture/compare registersComparatorA CATCTL2.7 CaoutCAF CACTL2.4CACTL2 Slope a/d conversionCACTL1 Caex Caon Caies Caifg Rsel REF1 REF0Peripheral file map Peripherals with Word AccessPeripherals with Byte Access MIN NOM MAX Units Absolute maximum ratings²Recommended operating conditions Frequency vs Supply Voltage MSP430x11x1 DevicesILPM3 Parameter Test Conditions MIN TYP MAX UnitIAM ILPM2Leakage current Outputs Port 1 to P2 P1.0 to P1.7, P2.0 to P2.5Port P1, P2 P1.x to P2.x Internal signals TAx, Smclk at TimerAInputs Px.x, TAx Parameter Test Conditions VCC MIN TYP MAX UnitComparatorA see Note Outputs P1.x, P2.x, TAxVRefVT vs Temperature, VCC = 2.2 V, C1121 VRefVT vs Temperature, VCC = 3 V, C1121CAF Caon PUC/PORParameter MIN NOM MAX Unit RAMDCO Steps DCOVariance Max DcoclkJTAG/programming Principle characteristics of the DCOWake-up from lower power modes LPMx GND Input/output schematicPort P1, P1.0 to P1.3, input/output with Schmitt-trigger P1IFG.5 P1IES.5 P1DIR.4 P1OUT.4 SmclkP1IFG.4 P1IES.4 P1DIR.5 P1OUT.5CAPD.X Port P2, P2.0 to P2.2, input/output with Schmitt-triggerP2DIR.4 P2OUT.4 Port P2, P2.3 to P2.4, input/output with Schmitt-triggerP2DIR.3 P2OUT.3 P2IFG.3 P1IES.3P2IRQ.5 P2SEL.5 VCCP2DIR.5 P2OUT.5Port P2, unbonded bits P2.6 and P2.7 PIN Shown Pins DIM MAXDW R-PDSO-G Plastic SMALL-OUTLINE Package15 NOM Gage Plane Seating Plane 20 MAX Pins ShownPins DIM MAX MIN PW R-PDSO-G Plastic SMALL-OUTLINE PackageImportant Notice