IBM 10 SP1 EAL4 Figure 5-34: Logical partitions, Figure 5-35: Machine state register

Figure 5-34: Logical partitions
On System p systems without logical partitions, the processor has two operating modes, user and supervisor.
The user and supervisor modes are implemented using the PR bit of the Machine State Register (MSR).
Logical partitions on System p systems necessitate a third mode of operation for the processor. This third
mode, called the hypervisor mode, provides all the partition control and partition mediation in the system. It
also affects access to certain instructions and memory areas. These operating modes for the processor are
implemented using the PR and HV bits of the MSR.
PR – Problem state.
•0 The processor is in privileged state (supervisor mode).
•1 The processor is in problem state (user mode).
HV – Hypervisor state.
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Figure 5-35: Machine state register