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IBM 10 SP1 EAL4 5.5.1 Four-Level Page Tables

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5.5.1 Four-Level Page Tables
Before the current implementation of four-level page tables, the kernel implemented a three-level page table
structure for all architectures. The three-level page table structure that previously existed was constituted,
from top to bottom, for the page global directory (PGD), page middle directory (PMD), and PTE.
In this implementation, the PMD is absent on systems that only present two-level page tables, so the kernel
was able to recognize all architectures as if they possessed three-level page tables.
The new page table structure actually implemented includes a new level, called PUD, immediately below the
top-level PGD directory. The PGD remains the top-level directory, and the PUD only exists on architectures
that are using four-level page tables. The PMD and PTE levels present the same function as in previous
kernels’ implementations. Each of the levels existent in a page table hierarchy is indexed with a subset of the
bits in the virtual address of interest.
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Figure 5-24: Previous three-level page-tables architecture

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