Intel 8XC251SB manuals
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Intel 8XC251SB Specifications
20 pages 564.52 Kb
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458 pages 2.59 Mb
5 CONTENTS21 CHAPTER 1 GUIDE TO THIS MANUAL33 CHAPTER 2 ARCHITECTURAL OVERVIEW34 2-2251 Microcontroller Core MCS Figure 2-1. Functional Block Diagram of the 8XC251SA, SB, SP, SQ 8XC251SA/SB/SP/SQ Microcontroller 43 CHAPTER 3 ADDRESS SPACES46 3-448 3-6Figure 3-4. 8XC251SA, SB, SP, SQ Address Space 49 i_mempar.fm5 Page 7 Thursday, June 27, 1996 1:38 PM3-7 Figure 3-5. Hardware Implementation of the 8XC251SA, SB, SP, SQ Address Space 51 53 3-11Figure 3-6. The Register File 55 i_mempar.fm5 Page 13 Thursday, June 27, 1996 2:06 PM 56 i_mempar.fm5 Page 14 Thursday, June 27, 1996 2:06 PM3-14 Figure 3-8. Dedicated Registers in the Register File and their Corresponding SFRs 57 i_mempar.fm5 Page 15 Thursday, June 27, 1996 2:06 PM59 3-17Table 3-5. 8XC251SA, SB, SP, SQ SFR Map and Reset Values 60 3-18Table 3-6. Core SFRs Table 3-7. I/O Port SFRs 61 3-19Table 3-8. Serial I/O SFRs Table 3-9. Timer/Counter and Watchdog Timer SFRs Table 3-10. Programmable Counter Array (PCA) SFRs 65 CHAPTER 4 DEVICE CONFIGURATION 67 4-3Figure 4-2. Configuration Array (External) 70 4-6Figure 4-3. Configuration Byte UCONFIG0 71 4-7Figure 4-4. Configuration Byte UCONFIG1 72 74 4-10Figure 4-5. Internal/External Address Mapping (RD1:0 = 00 and 01) 75 4-11Figure 4-6. Internal/External Address Mapping (RD1:0 = 10 and 11) 77 79 4-15Figure 4-7. Binary Mode Opcode Map Figure 4-8. Source Mode Opcode Map 83 CHAPTER 5 PROGRAMMING88 90 91 93 95 97 98 99 5-17Table 5-10. The Effects of Instructions on the PSW and PSW1 Flags 100 5-18Figure 5-2. Program Status Word Register 101 5-19Figure 5-3. Program Status Word 1 Register 105 CHAPTER 6 INTERRUPT SYSTEM106 6-2Figure 6-1. Interrupt Control System 108 6-4Table 6-3. Interrupt Control Matrix 110 6-6Figure 6-2. Interrupt Enable Register 111 x112 6-8Figure 6-3. Interrupt Priority High Register Figure 6-4. Interrupt Priority Low Register 114 123 CHAPTER 7 INPUT/OUTPUT PORTS125 7-3INPUT/OUTPUT PORTS Figure 7-2. Port 0 Structure Figure 7-1. Port 1 and Port 3 Structure 135 CHAPTER 8 TIMER/COUNTERS AND WATCHDOG TIMER136 8-2Figure 8-1. Basic Logic of the Timer/Counters Table 8-1. Timer/Counter and Watchdog Timer SFRs 141 8-7Figure 8-5. TMOD: Timer/Counter Mode Control Register 142 8-8Figure 8-6. TCON: Timer/Counter Control Register 149 8-15Figure 8-10. Timer 2: Clock Out Mode Table 8-3. Timer 2 Modes of Operation 150 151 8-17Figure 8-12. T2CON: Timer 2 Control Register 155 CHAPTER 9 PROGRAMMABLE COUNTER ARRAY156 157 i_pca.fm5 Page 3 Thursday, June 27, 1996 1:39 PM9-3 Figure 9-1. Programmable Counter Array 158 9-4Table 9-1. PCA Special Function Registers (SFRs) Table 9-2. External Signals 159 160 162 9-8Figure 9-3. PCA Software Timer and High-speed Output Modes 164 167 9-13Figure 9-7. CMOD: PCA Timer/Counter Mode Register 168 9-14Figure 9-8. CCON: PCA Timer/Counter Control Register Table 9-3. PCA Module Modes 169 x: PCA Compare/Capture Module Mode Registers 9-15 Figure 9-9. CCAPM 173 CHAPTER 10 SERIAL I/O PORT189 CHAPTER 11 MINIMUM HARDWARE SETUP199 CHAPTER 12 SPECIAL OPERATING MODES200 12-2Figure 12-1. Power Control (PCON) Register 201 12-3SPECIAL OPERATING MODES Figure 12-2. Idle and Powerdown Clock Control Table 12-1. Pin Conditions in Various Modes 204 209 CHAPTER 13 EXTERNAL MEMORY INTERFACE210 13-2Table 13-1. External Memory Interface Signals 211 212 i_extmem.fm5 Page 4 Thursday, June 27, 1996 1:39 PM213 215 13-7Figure 13-6. External Data Read (Page Mode) Figure 13-7. External Data Write (Page Mode) 217 13-9Figure 13-8. External Code Fetch (Nonpage Mode, One RD#/PSEN# Wait State) Figure 13-9. External Data Write (Nonpage Mode, One WR# Wait State) 221 13-13Figure 13-12. External Code Fetch/Data Read (Nonpage Mode, RT Wait State) Figure 13-13. External Data Write (Nonpage Mode, RT Wait State) 222 13-14Figure 13-14. External Data Read (Page Mode, RT Wait State) Figure 13-15. External Data Write (Page Mode, RT Wait State) 224 226 i_extmem.fm5 Page 18 Thursday, June 27, 1996 1:40 PM227 13-19Figure 13-18. Address Space for Example 1 230 13-22Figure 13-21. Bus Diagram for Example 3: 87C251SB/83C251SB in Nonpage Mode 231 13-23Figure 13-22. Address Space for Example 3 13-27 Figure 13-25. Bus Diagram for Example 5: 80C251SB in Nonpage Mode 235 236 13-28Figure 13-26. Address Space for Examples 5 and 6 241 CHAPTER 14 PROGRAMMING AND VERIFYING NONVOLATILE MEMORY 242 244 14-4Table 14-1. Programming and Verifying Modes 253 APPENDIX A INSTRUCTION SET REFERENCEi_opcode.fm5 Page 1 Thursday, June 27, 1996 1:41 PM 263 393 APPENDIX B SIGNAL DESCRIPTIONS439 GLOSSARY449 INDEX
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